Method of making SOI circuit with buried connectors

Claim 1

A method of manufacturing a CMOS integrated circuit having a plurality of N-channel and P-channel transistors formed in a silicon device layer, having a silicon device layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a set of mesa areas having a mesa top surface in said silicon layer; isolating said set of mesa areas from one another to form a set of mesas separated by a field area; forming said plurality of N-channel and P-channel transistors in said set of mesas; and connecting said plurality of N-channel and P-channel transistors to form an integrated circuit, characterized in that: a first silicon removal step removes a predetermined thickness of silicon from a first removal area; said first silicon removal step is followed by a step of performing a second silicon removal step in said field area overlapping said first silicon removal area, said second silicon removal step forming an isolation area in said silicon layer extending down toward said underlying insulator layer in said isolation area and extending down to a buried silicon connector in a buried connector area within said field area, thereby forming a buried silicon connector layer having a connector top surface below said mesa top surface in said buried connector area that is within said field area and outside said isolation area; covering said buried connector area with a field insulation layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements or said integrated circuit.

Claim 2

A method of manufacturing a CMOS integrated circuit having a plurality of N-channel and P-channel transistors formed in a silicon device layer, having a silicon device layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a set of mesa areas having a mesa top surface in said silicon layer; isolating said set of mesa areas from one another to form a set of mesas separated by a field area; forming said plurality of N-channel and P-channel transistors in said set of mesas; and connecting said plurality of N-channel and P-channel transistors to form an integrated circuit, characterized in that: a first silicon removal step removes a predetermined thickness of silicon from a first removal area; said first silicon removal step is followed by a step of performing a second silicon removal step in said field area overlapping said first silicon removal area, said second silicon removal step forming an isolation area in said silicon layer extending down toward said underlying insulator layer in said isolation area and extending down to a buried silicon connector in a buried connector area within said field area, thereby forming a buried silicon connector layer having a connector top surface below said mesa top surface in said buried connector area that is within said field area and outside said isolation area; covering said buried connector area with a field insulation layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements or said integrated circuit.

Claim 6

A method according to any of claims 1, 2, 3, or 4, further characterized in that; said first silicon removal step is an etching step and said second silicon removal step and said step of covering said buried connector with a field insulator are effected by a LOCOS step that converts silicon to an oxide field insulator.

Claim 7

A method according to any of claims 1, 2, 3, or 4, further characterized in that: said first and second silicon removal steps are both effected by first and second LOCOS steps, with an intermediate oxide removal step to remove oxide produced by said first LOCOS step.

Claim 8

A method of manufacturing an integrated circuit having a plurality of N-channel transistors formed in a silicon device layer, having a silicon device layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer; isolating said plurality of said mesa areas from one another to form a plurality of mesas separated by a field area; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: a first silicon removal step removes a predetermined thickness of silicon from an isolation area within said field area, whereby said silicon layer has a first thickness in said isolation area that is less than said silicon layer thickness; said first silicon removal step is followed by a step of performing a second silicon removal step in said field area overlapping said isolation area, said second silicon removal step forming a final field area in said silicon layer extending down to said underlying insulator layer in said isolation area and extending down to a buried silicon connector in a buried connector area within said field area, thereby forming a buried silicon connection layer having a connector top surface below said mesa top surface in a buried connection area that is within said field area and outside said isolation area; covering said buried connector area with a field insulation layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements of said integrated circuit.

Claim 9

A method of manufacturing an integrated circuit having a plurality of N-channel transistors formed in a silicon device layer, having a silicon device layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer; isolating said plurality of said mesa areas from one another to form a plurality of mesas separated by a field area; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: a first silicon removal step removes a predetermined thickness of silicon from an isolation area within said field area, whereby said silicon layer has a first thickness in said isolation area that is less than said silicon layer thickness; said first silicon removal step is followed by a step of performing a second silicon removal step in said field area overlapping said isolation area, said second silicon removal step forming a final field area in said silicon layer extending down to said underlying insulator layer in said isolation area and extending down to a buried silicon connector in a buried connector area within said field area, thereby forming a buried silicon connection layer having a connector top surface below said mesa top surface in a buried connection area that is within said field area and outside said isolation area; covering said buried connector area with a field insulation layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements of said integrated circuit.

Claim 15

A method of manufacturing an integrated circuit having a plurality of N-channel transistors formed in a silicon device layer, having a silicon device layer thickness, positioned above an underlying insulating layer comprising the steps of: defining a plurality of mesa areas in said silicon layer; performing a first LOCOS oxidation of a first area separating a plurality of said mesas from one another; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: said first LOCOS oxidation step forms a first field oxide layer having a first field oxide depth; said step of performing a first LOCOS oxidation is followed by a removal step of removing said first field oxide layer, whereby said silicon layer has a first thickness in said first field area that is less than said silicon layer thickness; said removal step is followed by a step of performing a second LOCOS oxidation step in a field area overlapping said first field area, said second LOCOS oxidation step forming a final field oxide layer that extends through said silicon layer down to said underlying insulator layer in said first field area and extends to a buried silicon connector in a buried connector area, whereby said final field oxide layer covers a buried silicon connection layer in a buried connection area that is within said field area and outside said first field area; and said buried connection layer is doped with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements of said integrated circuit.

Claim 16

A method of manufacturing an integrated circuit having a plurality of N-channel transistors formed in a silicon device layer, having a silicon device layer thickness, positioned above an underlying insulating layer comprising the steps of: defining a plurality of mesa areas in said silicon layer; performing a first LOCOS oxidation of a first area separating a plurality of said mesas from one another; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: said first LOCOS oxidation step forms a first field oxide layer having a first field oxide depth; said step of performing a first LOCOS oxidation is followed by a removal step of removing said first field oxide layer, whereby said silicon layer has a first thickness in said first field area that is less than said silicon layer thickness; said removal step is followed by a step of performing a second LOCOS oxidation step in a field area overlapping said first field area, said second LOCOS oxidation step forming a final field oxide layer that extends through said silicon layer down to said underlying insulator layer in said first field area and extends to a buried silicon connector in a buried connector area, whereby said final field oxide layer covers a buried silicon connection layer in a buried connection area that is within said field area and outside said first field area; and said buried connection layer is doped with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least two elements of said integrated circuit.

Claim 18

A method of manufacturing a silicon on insulator integrated circuit having a plurality of N-channel transistors formed in mesas in a silicon device layer having a silicon device layer thickness, positioned above an underlying insulating layer comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer by etching through said silicon device layer to said underlying insulating layer, thereby separating a plurality of said mesas from one another by a field area extending between said mesas; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: said step of defining said mesas comprises a step of forming a first field trench having a first field trench depth in an isolation area that is less than said field area and excludes a connector area; said step of defining said mesas further includes a step of thinning said silicon layer in said connector area, thereby forming a buried silicon connection layer having a top surface below said mesa top surface in a buried connector area that is within said field area and outside said isolation area and forming an insulating layer above said buried silicon connection layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least one body of one of said N-channel transistors and a voltage terminal.

Claim 19

A method of manufacturing a silicon on insulator integrated circuit having a plurality of N-channel transistors formed in mesas in a silicon device layer having a silicon device layer thickness, positioned above an underlying insulating layer comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer by etching through said silicon device layer to said underlying insulating layer, thereby separating a plurality of said mesas from one another by a field area extending between said mesas; forming said plurality of N-channel transistors in a corresponding plurality of mesas; and connecting said plurality of N-channel transistors to form an integrated circuit, characterized in that: said step of defining said mesas comprises a step of forming a first field trench having a first field trench depth in an isolation area that is less than said field area and excludes a connector area; said step of defining said mesas further includes a step of thinning said silicon layer in said connector area, thereby forming a buried silicon connection layer having a top surface below said mesa top surface in a buried connector area that is within said field area and outside said isolation area and forming an insulating layer above said buried silicon connection layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least one body of one of said N-channel transistors and a voltage terminal.

Claim 21

A method of manufacturing an SOI integrated circuit having a plurality of P-channel transistors formed in a silicon layer having a silicon layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer by etching through said silicon layer to said underlying insulating layer, thereby separating a plurality of said mesas from one another by a field area extending between said mesas; forming said plurality of P-channel transistors in a corresponding plurality of mesas; and connecting said plurality of P-channel transistors to form an integrated circuit, characterized in that: said step of defining said mesas comprises a step of forming a first field trench having a first field trench depth in an isolation area that is less than said field area and excludes a connector area; said step of defining said mesas further includes a step of thinning said silicon layer in said connector area, thereby forming a buried silicon connection layer having a top surface below said mesa top surface in a buried connector area that is within said field area and outside said isolation area and forming an insulating layer above said buried silicon connection layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least one body of one of said N-channel transistors and a voltage terminal.

Claim 22

A method of manufacturing an SOI integrated circuit having a plurality of P-channel transistors formed in a silicon layer having a silicon layer thickness and positioned above an underlying insulating layer, comprising the steps of: defining a plurality of mesa areas having a mesa top surface in said silicon layer by etching through said silicon layer to said underlying insulating layer, thereby separating a plurality of said mesas from one another by a field area extending between said mesas; forming said plurality of P-channel transistors in a corresponding plurality of mesas; and connecting said plurality of P-channel transistors to form an integrated circuit, characterized in that: said step of defining said mesas comprises a step of forming a first field trench having a first field trench depth in an isolation area that is less than said field area and excludes a connector area; said step of defining said mesas further includes a step of thinning said silicon layer in said connector area, thereby forming a buried silicon connection layer having a top surface below said mesa top surface in a buried connector area that is within said field area and outside said isolation area and forming an insulating layer above said buried silicon connection layer; and doping said buried connection layer with a predetermined dopant to establish a predetermined buried layer conductivity in at least one connector area between at least one body of one of said N-channel transistors and a voltage terminal.