CMOS structure for eliminating latch-up of parasitic thyristor

Claim 1

A complementary metal oxide semiconductor device comprising: a substrate having a top surface and comprising a first semiconductor material doped to a first conductivity type; a first field effect transistor including a first channel region defined in said substrate, a first source region provided on said substrate adjacent to said first channel region and doped to a second, opposite conductivity type, a first drain region doped to said second conductivity type and provided on said substrate adjacent to said first channel region such that said first channel region is formed between said first source region and said first drain region, and a gate electrode provided on the substrate above said first channel region; a well defined in a portion of said substrate, extending to the top surface thereof and excluding the first channel region, the first source region and the first drain region, said well being doped to said second conductivity type; a second field effect transistor including a second channel region defined in said well, a second source region provided on said well adjacent to said second channel region and doped to said first conductivity type, a second drain region doped to said first conductivity type and provided on said well adjacent to said second channel region such that said second channel region is formed between said second source region and said second drain region in the well, and a second gate electrode provided on the well above said second channel region; and at least one of said first and second source regions being made of a second semiconductor material having a band gap substantially narrower than the band gap of said first semiconductor material, said second semiconductor material being provided on the top surface of the substrate in a state such that a strain is induced in said second semiconductor material.