← Back to Patent Explorer
US4635089A Expired / Lapsed US ⏱️ 0.0 years remaining

MIS-integrated semiconductor device

Assignee: Seiko Instruments Inc
•
Filing: 1986-02-19
•
Granted: 1987-01-06
•
Expires: 2006-02-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The present invention aims to form a MOST, for example a MOS-SIT, whose impurity density in a channel region is lower than an ordinary MOST on a substrate or is formed in an epitaxial growth layer on a well.

Inventors

  • 👤 Masafumi Shimbo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 14:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/83138; H10D84/85; H10D84/856; H10D88/00

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 258 words
A MIS integrated semiconductor device comprising: one chip having thereon a first MIS transistor comprising an insulating gated field effect MIS transistor having a first channel region of one conduction type comprising a portion of a first well of the one conduction type formed in a substrate crystal of an opposite conduction type to said one conduction type, first source and drain regions of said opposite conduction type formed in said first well, a first gate insulating film on said first channel region and a first gate electrode on said first gate insulating film, and also on the one chip a second MIS transistor comprising a MIS static induction transitor having a second channel region of said one conduction type with an impurity concentration lower than that of said first channel region, second source and drain regions of said opposite conduction type formed in said second channel region in spaced-apart relation along the length direction thereof, a second gate insulating film on said second channel region, and a second gate electrode on said second gate insulating film and having a narrower width in said length direction than the length of said second channel region between said second source and drain regions, wherein said second channel region comprises a solid-phase epitaxial layer grown on a second well of said one conduction type formed simultaneously with said first well or on an elongated portion of said first well and has an impurity concentration determined by the impurity diffusion from said second well or said elongated portion of said first well.
Claim 2
Dependent Claim 258 words
A MIS integrated semiconductor device comprising: one chip having thereon a first MIS transistor comprising an insulating gated field effect MIS transistor having a first channel region of one conduction type comprising a portion of a first well of the one conduction type formed in a substrate crystal of an opposite conduction type to said one conduction type, first source and drain regions of said opposite conduction type formed in said first well, a first gate insulating film on said first channel region and a first gate electrode on said first gate insulating film, and also on the one chip a second MIS transistor comprising a MIS static induction transitor having a second channel region of said one conduction type with an impurity concentration lower than that of said first channel region, second source and drain regions of said opposite conduction type formed in said second channel region in spaced-apart relation along the length direction thereof, a second gate insulating film on said second channel region, and a second gate electrode on said second gate insulating film and having a narrower width in said length direction than the length of said second channel region between said second source and drain regions, wherein said second channel region comprises a solid-phase epitaxial layer grown on a second well of said one conduction type formed simultaneously with said first well or on an elongated portion of said first well and has an impurity concentration determined by the impurity diffusion from said second well or said elongated portion of said first well.
Claim 3
Dependent Claim 211 words
A MIS integrated semiconductor device according to claim 1; wherein the one chip also has thereon a third MIS transistor having a third channel region of said opposite conduction type comprising a portion of said substrate, third source and drain regions of said one conduction type formed in said substrate, a third gate insulating film on said third channel region and a third gate electrode on said third gate insulating film and also on the chip a fourth MIS transistor comprising a MIS static induction transistor having a fourth channel region of said opposite conduction type with an impurity concentration lower than that of said third channel region, fourth source and drain regions of said one conduction type formed in said fourth channel region in spaced-apart relation along the length direction thereof, a fourth gate insulating film on said fourth channel region, and a fourth gate electrode on said fourth gate insulating film and having a narrower width in said length direction than the length of said fourth channel region between said fourth source and drain regions, wherein said fourth channel region comprises a solid-phase epitaxial layer grown on said substrate simultaneously formed with said second channel region and has an impurity concentration determined by the impurity diffusion from said substrate.

References Cited (Backward Citations)

CA930477A Cited
US4161417A Cited
JPS53118986A Cited
US4472871A Cited
JPS5562771A Cited
JPS5574172A Cited
JPS55105361A Cited
WO1981000489A1 Cited
JPS5662356A Cited
US4487639A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-01-05 1990-07-07 1991-01-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-01-05 1994-07-07 1995-01-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-01-05 1998-07-07 1999-01-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag