Patent US5136354A successfully refreshed from Google Patents.
US5136354A
Expired / Lapsed
US
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Semiconductor device wafer with interlayer insulating film covering the scribe lines
Assignee: Seiko Epson Corp
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Filing: 1990-04-12
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Granted: 1992-08-04
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Expires: 2010-04-12
Abstract
Abstract A semiconductor device wafer in which the interlayer insulating film between wirings and the passivation film formed during the manufacturing process are left on the entire surface of the scribe line area during dicing. The interlayer insulating film between wirings and the passivation film formed during the manufacturing process may be left on most of the scribe line area, in which case a slit groove is provided along the periphery of a chip and the passivation film is removed at the location of the slit groove. Alternatively, the passivation film formed during the manufacturing process may be left on a part of the scribe line area where a film structure is provided. In this case, a slit groove is provided along the periphery of a chip and the passivation film is removed at the location of the slit groove in the same way as mentioned above on the part of the scribe line in which there is a film structure such as an alignment mark, while most of the passivation film on the scribe lines is removed in the area in which there is no film structure.
Inventors
- 👤 Naoyuki Morita
- 👤 Hiroaki Tsugane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:39
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10P; H10P52/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
148 words
An integrated circuit wafer comprising a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, wherein said chip has at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and said wafer comprises at least one interlayer insulation film having portions which extend across each said chip and interposed between two of said layers of electrically conductive material to form a component part of each said element, said interlayer insulation film further having portions which extend across the entirety of said scribe lines at the time said substrate is cut along said scribe lines and which are contiguous with portions of said interlayer insulation film that extend across each said chip.
Claim 2
Dependent Claim
148 words
An integrated circuit wafer comprising a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, wherein said chip has at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and said wafer comprises at least one interlayer insulation film having portions which extend across each said chip and interposed between two of said layers of electrically conductive material to form a component part of each said element, said interlayer insulation film further having portions which extend across the entirety of said scribe lines at the time said substrate is cut along said scribe lines and which are contiguous with portions of said interlayer insulation film that extend across each said chip.
Claim 3
Dependent Claim
22 words
A wafer as defined in claim 1 further comprising a passivation film covering said chips and the entirety of said scribe lines.
Claim 4
Dependent Claim
56 words
A wafer as defined in claim 1 wherein each scribe line has two longitudinal edges, and further comprising a passivation film covering said interlayer insulation film over at least portions of said chips and said scribe line regions, said passivation films having at least one groove formed along at least one edge of each scribe line.
Claim 5
Dependent Claim
23 words
A wafer as defined in claim 3 wherein said passivation film has a respective groove formed along each edge of each scribe line.
Claim 6
Dependent Claim
106 words
A wafer as defined in claim 1 wherein: each scribe lines has two longitudinal edges, and further comprising: a film having a defined pattern located at at least one scribe line region above said interlayer insulation film and spaced inwardly of said two longitudinal edges; and a passivation film covering said chips and the at least one scribe line region, said passivation film having, at the at least one scribe line region, at least one groove formed along at least one edge of the scribe line, and said passivation film being absent from scribe line regions where said film having a defined pattern is not present.
Claim 7
Dependent Claim
31 words
A wafer as defined in claim 5 wherein said passivation film at said at least one scribe line region has a respective groove formed along each edge of the scribe line.
Claim 8
Dependent Claim
20 words
A wafer as defined in claim 1 wherein said interlayer insulation film directly contacts said substrate regions constituting scribe lines.
Claim 9
Dependent Claim
35 words
A wafer as defined in claim 7 wherein the surface of said substrate is initially planar and the substrate surface regions constituting said scribe lines constitute portions of the initially planar surface of said substrate.
Claim 10
Dependent Claim
35 words
A wafer as defined in claim 1 wherein the surface of said substrate is initially planar and the substrate surface regions constituting said scribe lines constitute portions of the initially planar surface of said substrate.
Claim 11
Independent Claim
183 words
A method of dicing an integrated circuit comprising a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, wherein each chip has at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and said wafer comprises at least one interlayer insulation film having portions which extend across each said chip and interposed between two of said layers of electrically conductive material to form a component part of each said element, said interior insulation film further having portions which extend across the entirety of said scribe lines at the time said substrate is cut along said scribe lines and which are contiguous with portions of said interlayer insulation film that extend across each said chip, said method being performed to separate the chips from one another, and comprising scribing the wafer along the scribe lines while the interlayer insulation film is present on the scribe line regions.
Claim 12
Independent Claim
183 words
A method of dicing an integrated circuit comprising a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, wherein each chip has at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and said wafer comprises at least one interlayer insulation film having portions which extend across each said chip and interposed between two of said layers of electrically conductive material to form a component part of each said element, said interior insulation film further having portions which extend across the entirety of said scribe lines at the time said substrate is cut along said scribe lines and which are contiguous with portions of said interlayer insulation film that extend across each said chip, said method being performed to separate the chips from one another, and comprising scribing the wafer along the scribe lines while the interlayer insulation film is present on the scribe line regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |