US4925808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making IC die with dielectric isolation
Assignee: Allegro Microsystems LLC
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Filing: 1989-03-24
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Granted: 1990-05-15
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Expires: 2009-03-24
Abstract
Abstract The method includes forming in one surface of an N+ silicon wafer a matrix of uniformly deep V-shaped grooves, growing one SiO 2 over the one surface and the walls of the grooves, forming over the opposite wafer surface a thick self-supporting polycrystalline layer, progressively removing portions of the original silicon wafer until the bottoms of the grooves are detected to leave separate patches of the original N+ silicon wafer material and then growing a thin (e.g. 6 microns) P-doped layer of epitaxial silicon on the exposed N+ silicon layer patch portions now isolated and defined by the grooves. A figure-eight pattern of trenches is formed in each silicon island completely through the P epitaxial layer and each of the underlying N+ buried patches but stopped at the SiO 2 layer. An N+ plug is formed through the epitaxial layer to each N+ patch. Metal conductors complete the formation of a JFET transistor in each island bounded and defined by one of the closed loops or annular portions of the figure-eight-patterned trenches. The wafer is then sawed apart along all the V-shaped grooves providing a plurality of IC die, each having two dielectrically isolated JFET transistors.
Inventors
- 👤 William E. Richardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:15
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D86/00; H10D86/01; H10D86/021; H10D86/0251; H10P; H10P54/00; H10W10/01; H10W10/011; H10W10/019
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
237 words
A method for making integrated-circuit die with dielectric isolation comprising: (a) forming a network of rows and columns of V-shaped grooves in one major surface of a single-crystal silicon wafer to divide said surface into a plurality of die-surface areas, each being bounded by said grooves: (b) forming a first dielectric layer over said one surface and the walls of said grooves; (c) depositing a thick polysilicon layer capable of being self-supporting over said first dielectric layer; (d) progressively removing original strata of said single-crystal silicon wafer at the opposite major wafer surface until a bottom portion of said grooves is also removed revealing patches of a thin non-self-supporting layer of said single-crystal silicon wafer between said rows and said columns, so that said patches are supported by said dielectric layer that is in turn supported by said polysilicon layer; (e) growing a silicon epitaxial layer over the exposed surface of said single-crystal silicon patches; (f) forming in each of said die-surface areas trenches in a figure-eight pattern that penetrate completely through both said silicon epitaxial layer and the underlying of said silicon patches to create two spaced apart silicon islands, each bounded entirely by said trenches; (g) forming a dielectric layer over said epitaxial layer and the walls of said trenches; and (h) separating said wafer along the center lines of said grooves to produce a plurality of die each having two dielectrically isolated silicon islands.
Claim 2
Independent Claim
237 words
A method for making integrated-circuit die with dielectric isolation comprising: (a) forming a network of rows and columns of V-shaped grooves in one major surface of a single-crystal silicon wafer to divide said surface into a plurality of die-surface areas, each being bounded by said grooves: (b) forming a first dielectric layer over said one surface and the walls of said grooves; (c) depositing a thick polysilicon layer capable of being self-supporting over said first dielectric layer; (d) progressively removing original strata of said single-crystal silicon wafer at the opposite major wafer surface until a bottom portion of said grooves is also removed revealing patches of a thin non-self-supporting layer of said single-crystal silicon wafer between said rows and said columns, so that said patches are supported by said dielectric layer that is in turn supported by said polysilicon layer; (e) growing a silicon epitaxial layer over the exposed surface of said single-crystal silicon patches; (f) forming in each of said die-surface areas trenches in a figure-eight pattern that penetrate completely through both said silicon epitaxial layer and the underlying of said silicon patches to create two spaced apart silicon islands, each bounded entirely by said trenches; (g) forming a dielectric layer over said epitaxial layer and the walls of said trenches; and (h) separating said wafer along the center lines of said grooves to produce a plurality of die each having two dielectrically isolated silicon islands.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein said growing said epitaxial layer is stopped before the thickness of said epitaxial layers exceeds 9 microns.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said one major surface of said wafer is in the 100 silicon crystal plane.
Claim 5
Dependent Claim
56 words
The method of claim 3 wherein said forming said V-shaped grooves is accomplished by forming a first mask having apertures positioned over regions of said one wafer surface at which said grooves are to be formed, and selectively isotropically etching through said apertures so that said etching is self-stopped when said V-shaped grooves are completely formed.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said grooves in each said column and row, consist of a series of spaced apart short grooves.
Claim 7
Dependent Claim
46 words
The method of claim 5 wherein said first mask apertures are organized in groups of from 3 to 5 apertures having different predetermined widths, said subsequent isotropically etching leading to different self-stopped depths of a group of corresponding of said short grooves after said isotropic etching.
Claim 8
Dependent Claim
42 words
The method of claim 6 wherein said removing is stopped after the largest of said short grooves but not the shortest of said grooves in said groups of grooves over the entire surface of said wafer have been revealed by said removing.
Claim 9
Dependent Claim
14 words
The method of claim 1 wherein said separating said wafer is accomplished by sawing.
Claim 10
Dependent Claim
13 words
The method of claim 1 wherein said mechanically removing is accomplished by lapping.
Claim 11
Dependent Claim
37 words
The method of claim 1 wherein said single-crystal silicon wafer is heavily doped with impurities of one polarity type, and said growing said epitaxial layer includes doping said epitaxial layer with impurities of the other polarity type.
Claim 12
Dependent Claim
32 words
The method of claim 10 additionally comprising forming two essentially identical JFET transistors, respectively, in said two silicon islands wherein said heavily doped silicon patch in each island serves as the gate.
Claim 13
Dependent Claim
88 words
The method of claim 10 wherein said forming said JFET transistors is accomplished simultaneously for each of said transistors by forming a gate-contact plug region through said epitaxial layer portion in each said island by selectively doping with impurities of the one type, forming a metal ohmic contact via said plug to said thin silicon patch serving as the transistor gate and forming a metal Schottky source contact and a metal Schottky drain contact through spaced apart holes in said silicon dioxide layer to said epitaxial layer surface.
Claim 14
Dependent Claim
202 words
In a process for making an integrated semiconductor circuit of the kind including forming in one surface of a single-crystal semiconductor wafer a network of rows and columns of uniformly deep grooves, forming one insulating layer over said one surface and over the walls of said grooves, forming over the opposite wafer surface a thick self-supporting polysilicon layer, progressively removing portions of said single-crystal semiconductor material until the bottoms of at least portions of said grooves are removed and growing a thin epitaxial layer over the remaining exposed single-crystal material, the improvement comprising: (a) forming at each patch of said epitaxial layer delineated by adjacent of said rows and columns, a figure-eight pattern of trenches completely through said epitaxial layer and said single-crystal semiconductor material, but not through said one insulating layer so that two islands made up of portions of said semiconductor material and said epitaxial layer are each separated by and surrounded by said trenches; (b) forming another insulating layer over said epitaxial layer portions and the walls of said trenches; (c) forming a transistor in each of said two semiconductor islands; and (d) separating said wafer along said grooves to produce individual die with two dielectrically isolated semiconductor islands.
Claim 15
Dependent Claim
202 words
In a process for making an integrated semiconductor circuit of the kind including forming in one surface of a single-crystal semiconductor wafer a network of rows and columns of uniformly deep grooves, forming one insulating layer over said one surface and over the walls of said grooves, forming over the opposite wafer surface a thick self-supporting polysilicon layer, progressively removing portions of said single-crystal semiconductor material until the bottoms of at least portions of said grooves are removed and growing a thin epitaxial layer over the remaining exposed single-crystal material, the improvement comprising: (a) forming at each patch of said epitaxial layer delineated by adjacent of said rows and columns, a figure-eight pattern of trenches completely through said epitaxial layer and said single-crystal semiconductor material, but not through said one insulating layer so that two islands made up of portions of said semiconductor material and said epitaxial layer are each separated by and surrounded by said trenches; (b) forming another insulating layer over said epitaxial layer portions and the walls of said trenches; (c) forming a transistor in each of said two semiconductor islands; and (d) separating said wafer along said grooves to produce individual die with two dielectrically isolated semiconductor islands.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |