US5136349A
Expired / Lapsed
US
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Closed cell transistor with built-in voltage clamp
Assignee: Vishay Siliconix Inc
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Filing: 1990-10-12
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Granted: 1992-08-04
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Expires: 2010-10-12
Abstract
Abstract A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.
Inventors
- 👤 Hamza Yilmaz
- 👤 Izak Bencuya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/411; H10D12/441; H10D18/00; H10D18/60; H10D18/65; H10D18/655; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/108; H10D62/124; H10D62/125; H10D62/126; H10D62/127; H10D62/17; H10D62/393; H10D84/00; H10D84/101; H10D84/141; H10D84/148; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
156 words
A transistor comprising a plurality of cells wherein each cell comprises: a semiconductor body of a first conductivity type; a substantially annular first region of a second conductivity type formed in the semiconductor body and surrounding a portion of the semiconductor body at a principal surface of the semiconductor body; a second region of the first conductivity type formed in the annular region; a conductive gate region overlying the principal surface of the semiconductor body and having its extent defined by the surrounded portion of the semiconductor body; and a clamping region of the second conductivity type formed in the surrounded portion of the semiconductor body, and having a voltage breakdown lower than a voltage breakdown of a the annular first region and second region, wherein the clamping region has a cross-sectional shape differing from that of the annular firs region and a depth and doping level the same as that of the annular first region.
Claim 2
Dependent Claim
156 words
A transistor comprising a plurality of cells wherein each cell comprises: a semiconductor body of a first conductivity type; a substantially annular first region of a second conductivity type formed in the semiconductor body and surrounding a portion of the semiconductor body at a principal surface of the semiconductor body; a second region of the first conductivity type formed in the annular region; a conductive gate region overlying the principal surface of the semiconductor body and having its extent defined by the surrounded portion of the semiconductor body; and a clamping region of the second conductivity type formed in the surrounded portion of the semiconductor body, and having a voltage breakdown lower than a voltage breakdown of a the annular first region and second region, wherein the clamping region has a cross-sectional shape differing from that of the annular firs region and a depth and doping level the same as that of the annular first region.
Claim 3
Dependent Claim
30 words
The device of claim 1 wherein the annular first region and the second region are substantially square in shape in plane defined by the principal surface of the semiconductor body.
Claim 4
Dependent Claim
30 words
The device of claim 1 wherein the clamping region is of a spherical shape in a plane perpendicular to a plane defined by the principal surface of the semiconductor body.
Claim 5
Dependent Claim
18 words
The device of claim 1 wherein the annular first region and the semiconductor body form a graded junction.
Claim 6
Dependent Claim
34 words
The device of claim 1 wherein the transistor further comprises a substrate of the second conductivity type underlying the semiconductor body, and the clamping region, substrate, and semiconductor body form a bipolar junction transistor.
Claim 7
Dependent Claim
32 words
The device of claim 1 wherein the transistor further comprises a substrate of the first conductivity type underlying the semiconductor body, and the clamping region and semiconductor body form a zener diode.
Claim 8
Dependent Claim
23 words
The device of claim 1, further comprising a portion of the conductive gate region being the conductive gate region of an adjacent cell.
Claim 9
Dependent Claim
41 words
The device of claim 7, wherein the conductive gate region of a first cell comprises a layer of polycrystalline silicon connected to the conductive gate region of at least one adjoining cell by an extension of the layer of polycrystalline silicon.
Claim 10
Dependent Claim
18 words
The device of claim 1 wherein the annular first region forms a graded junction with the semiconductor body.
Claim 11
Dependent Claim
160 words
An insulated gate bipolar transistor comprising a plurality of cells, wherein each cell comprises: a substrate having a first conductivity type; a first region of a second conductivity type overlying the substrate; a substantially annular second region of the first conductivity type formed in the first region and surrounding a portion of the first region at a principal surface thereof; at least one third region having the second conductivity type formed in the annular region; a conductive gate region overlying the surrounded portion of the first region; and a fourth region of the first conductivity type formed in the surrounded portion of the first region wherein the fourth region is a clamping region, and wherein the fourth region has a cross-sectional shape differing from that of the annular second region and a depth and a doping level the same as that of the annular second region, and wherein the fourth region, first region, and substrate form a bipolar junction transistor.
Claim 12
Dependent Claim
160 words
An insulated gate bipolar transistor comprising a plurality of cells, wherein each cell comprises: a substrate having a first conductivity type; a first region of a second conductivity type overlying the substrate; a substantially annular second region of the first conductivity type formed in the first region and surrounding a portion of the first region at a principal surface thereof; at least one third region having the second conductivity type formed in the annular region; a conductive gate region overlying the surrounded portion of the first region; and a fourth region of the first conductivity type formed in the surrounded portion of the first region wherein the fourth region is a clamping region, and wherein the fourth region has a cross-sectional shape differing from that of the annular second region and a depth and a doping level the same as that of the annular second region, and wherein the fourth region, first region, and substrate form a bipolar junction transistor.
Claim 13
Dependent Claim
34 words
The device of claim 10, further comprising a region of the second conductivity type formed between the substrate and the first region and having a higher concentration of charges than does the first region.
Claim 14
Dependent Claim
18 words
The device of claim 10 wherein the annular second region forms a graded junction with the first region.
Claim 15
Dependent Claim
143 words
A DMOS transistor comprising a plurality of cells, wherein each cell comprises: a substrate having a first conductivity type; a first region of the first conductivity type overlying the substrate; an annular second region of a second conductivity type formed in the first region and surrounding a portion of the first region at a principal surface thereof; at least one second region having the first conductivity type formed in the annular region; a conductive gate region overlying the surrounded portion of the first region; and a third region of the second conductivity type formed in the surrounded portion of the first region, wherein the third region is a clamping region, and wherein the third region has a cross-sectional shape differing from that of the annular second region and a depth and a doping level the same as that of the annular second region.
Claim 16
Dependent Claim
143 words
A DMOS transistor comprising a plurality of cells, wherein each cell comprises: a substrate having a first conductivity type; a first region of the first conductivity type overlying the substrate; an annular second region of a second conductivity type formed in the first region and surrounding a portion of the first region at a principal surface thereof; at least one second region having the first conductivity type formed in the annular region; a conductive gate region overlying the surrounded portion of the first region; and a third region of the second conductivity type formed in the surrounded portion of the first region, wherein the third region is a clamping region, and wherein the third region has a cross-sectional shape differing from that of the annular second region and a depth and a doping level the same as that of the annular second region.
Claim 17
Dependent Claim
34 words
The device of claim 12, further comprising a region of the second conductivity type formed between the substrate and the first region and having a higher concentration of charges than does the first region.
Claim 18
Dependent Claim
34 words
The device of claim 13, further comprising a region of the first conductivity type formed between the substrate and the first region and having a higher concentration of charges than does the first region.
Claim 19
Dependent Claim
197 words
A transistor comprising a plurality of cells wherein each cell comprises: a semiconductor body of a first conductivity type; a substantially annular first region of the first conductivity type formed in the semiconductor body and surrounding a portion of the semiconductor body at a principal surface of the semiconductor body; a substantially annular second region of a second conductivity type formed in the semiconductor body and surrounding the annular first region; a conductive gate region overlying the principal surface of the semiconductor body and having its extent defined by the surrounded portion of the semiconductor body, a portion of the gate region overlying portions of both the annular first region and annular second region, and being in physical contact with a gate region of an adjacent cell; and at least one clamping region of the second conductivity type formed in the surrounded portion of the semiconductor body, and having a voltage breakdown lower than a voltage breakdown of the annular first region and annular second region, wherein the clamping region has a cross-sectional shape differing from that of the annular second region and a depth and doping level the same as that of the annular second region.
Claim 20
Dependent Claim
197 words
A transistor comprising a plurality of cells wherein each cell comprises: a semiconductor body of a first conductivity type; a substantially annular first region of the first conductivity type formed in the semiconductor body and surrounding a portion of the semiconductor body at a principal surface of the semiconductor body; a substantially annular second region of a second conductivity type formed in the semiconductor body and surrounding the annular first region; a conductive gate region overlying the principal surface of the semiconductor body and having its extent defined by the surrounded portion of the semiconductor body, a portion of the gate region overlying portions of both the annular first region and annular second region, and being in physical contact with a gate region of an adjacent cell; and at least one clamping region of the second conductivity type formed in the surrounded portion of the semiconductor body, and having a voltage breakdown lower than a voltage breakdown of the annular first region and annular second region, wherein the clamping region has a cross-sectional shape differing from that of the annular second region and a depth and doping level the same as that of the annular second region.
Claim 21
Dependent Claim
14 words
The transistor of claim 16, wherein each cell includes a plurality of clamping regions.
Claim 22
Dependent Claim
21 words
The transistor of claim 16, wherein the gate region is in physical contact with the gate region of each adjacent cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-04 | 1996-02-03 | 1996-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-04 | 2000-02-03 | 2000-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-04 | 2004-02-03 | 2004-08-04 | $7700.00 | Window Closed / Lapsed |