US4775879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FET structure arrangement having low on resistance
Assignee: Semiconductor Components Industries LLC
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Filing: 1987-03-18
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Granted: 1988-10-04
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Expires: 2007-03-18
Abstract
Abstract A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.
Inventors
- 👤 Stephen P. Robb
- 👤 Lewis E. Terry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D10/00; H10D10/40; H10D30/01; H10D30/021; H10D30/025; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
161 words
A vertical field effect transistor having a plurality of source areas which are arranged in a pattern to achieve minimum inactive drain area, comprising: a semiconductor substrate having a first surface and a second surface; the plurality of source areas being substantially square in configuration and extending into the substrate from the first surface; a region surrounding each of the plurality of source areas and extending into the substrate a greater distance than the source areas; a common drain electrode in contact with the second surface; the plurality of source areas being arranged in rows and columns wherein every other row is offset from an adjacent row in order that a source in the offset row is aligned with a space provided between two source areas in the adjacent row and the distance between an offset row and an adjacent row is one-half the distance between source areas in the same row; and a gate electrode formed between adjacent source areas.
Claim 2
Dependent Claim
161 words
A vertical field effect transistor having a plurality of source areas which are arranged in a pattern to achieve minimum inactive drain area, comprising: a semiconductor substrate having a first surface and a second surface; the plurality of source areas being substantially square in configuration and extending into the substrate from the first surface; a region surrounding each of the plurality of source areas and extending into the substrate a greater distance than the source areas; a common drain electrode in contact with the second surface; the plurality of source areas being arranged in rows and columns wherein every other row is offset from an adjacent row in order that a source in the offset row is aligned with a space provided between two source areas in the adjacent row and the distance between an offset row and an adjacent row is one-half the distance between source areas in the same row; and a gate electrode formed between adjacent source areas.
Claim 3
Dependent Claim
29 words
The vertical field effect transistor of claim 1 wherein the source areas have sides of the same length as the distance between adjacent source areas in the same row.
Claim 4
Dependent Claim
56 words
A vertical field effect transistor having a common drain and parallel connected sources and gates, the sources being arranged wherein distance between sources in a first direction is less than the distance between sources in a second direction to substantially leave no inactive drain area between the sources during operation of the vertical field effect transistor.
Claim 5
Dependent Claim
56 words
A vertical field effect transistor having a common drain and parallel connected sources and gates, the sources being arranged wherein distance between sources in a first direction is less than the distance between sources in a second direction to substantially leave no inactive drain area between the sources during operation of the vertical field effect transistor.
Claim 6
Dependent Claim
31 words
The vertical field effect transistor of claim 3 wherein the distance between the sources in the first direction is approximately one-half of the distance between the sources in the second direction.
Claim 7
Dependent Claim
14 words
The vertical field effect transistor of claim 3 wherein the sources are substantially square.
Claim 8
Dependent Claim
106 words
A vertical FET semiconductor device having a plurality of source areas on one surface of a semiconductor substrate and a drain electrode on the opposite surface of the semiconductor substrate, comprising an arrangement of the source areas to substantially eliminate inactive drain area on the one surface of the semiconductor substrate wherein the source areas are rectangular in shape and form columns and rows in the arrangement, wherein every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row, and the rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area.
Claim 9
Dependent Claim
106 words
A vertical FET semiconductor device having a plurality of source areas on one surface of a semiconductor substrate and a drain electrode on the opposite surface of the semiconductor substrate, comprising an arrangement of the source areas to substantially eliminate inactive drain area on the one surface of the semiconductor substrate wherein the source areas are rectangular in shape and form columns and rows in the arrangement, wherein every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row, and the rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area.
Claim 10
Dependent Claim
13 words
The vertical FET of claim 6 having its gate on the one surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-04 | 1992-04-04 | 1992-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-04 | 1996-04-04 | 1996-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-04 | 2000-04-04 | 2000-10-04 | $7700.00 | Window Closed / Lapsed |