Semiconductor device comprising a DMOSFET

Claim 2

A semiconductor device having a MOSFET (QM1) having a source (S), a drain (D), a gate (G) and a channel base region (14a, 14b), characterized by a diode (D3) having an anode and a cathode between which current path of said MOSFET (QMl) is formed, said diode (D3) having a set forward voltage drop lower than that of a parasitic diode (Dl) formed by the junction between said channel base region (14a, 14b) of said MOSFET and a source region (12) thereof.

Claim 3

A semiconductor device comprising a high impurity concentration semiconductor substrate (11) of a first conductivity type, a low impurity concentration epitaxial layer (12) formed on one surface of said semiconductor substrate (11), a drain electrode (13) formed on the other surface of said semiconductor substrate (11), a first and second channel base region (14a, 14b) of a second conductivity type formed at a predetermined distance from each other in said low impurity concentration epitaxial layer (12), a first and second high impurity concentration source region (15a, 15b) of the first conductivity type formed in said respective first and second channel base regions (14a, 14b), a gate oxide film (16) formed on said low impurity concentration epitaxial layer (12) between said first and second channel base regions (14a, 14b), a gate electrode (17) formed on said gate oxide film (16) and an insulation film (18) formed on said gate electrode (17), characterized by an impurity diffusion region (20) of the second conductivity type formed in said low impurity concentration epitaxial layer (12) and constituting a diode (D3), and a source electrode (19) formed on said insulation film (18), channel base regions (14a, 14b), source regions (15a, 15b) and a second conductivity type impurity diffusion region (20) constituting said diode.

Claim 4

A semiconductor device comprising a high impurity concentration semiconductor substrate (11) of a first conductivity type, a low impurity concentration epitaxial layer (12) formed on one surface of said semiconductor substrate (11), a drain electrode (13) formed on the other surface of said semiconductor substrate (11), a first and second channel base region (14a, 14b) of a second conductivity type formed at a predetermined distance from each other in said low impurity concentration epitaxial layer (12), a first and second high impurity concentration source region (15a, 15b) of the first conductivity type formed in said respective first and second channel base regions (14a, 14b), a gate oxide film (16) formed on said low impurity concentration epitaxial layer (12) between said first and second channel base regions (14a, 14b), a gate electrode (17) formed on said gate oxide film (16) and an insulation film (18) formed on said gate electrode (17), characterized by an impurity diffusion region (20) of the second conductivity type formed in said low impurity concentration epitaxial layer (12) and constituting a diode (D3), and a source electrode (19) formed on said insulation film (18), channel base regions (14a, 14b), source regions (15a, 15b) and a second conductivity type impurity diffusion region (20) constituting said diode.

Claim 5

The semiconductor device according to claim 2, characterized by burrier layers (10a, lOb) formed in contact areas between said first and second channel base regions (14a, 14b) and first and second source regions (15a, 15b) and said source region (19).

Claim 6

The semiconductor device according to claim 2, characterized in that said second conductivity type impurity diffusion region (20) constituting said diode (D3) is formed at a predetermined distance from said first and second channel base regions (14a, 14b) and that an insulation film (18) is formed on said low impurity concentration epitaxial layer (12) between said channel base region (14a) and impurity diffusion region (20).

Claim 7

The semiconductor device according to claim 2, characterized in that said second conductivity type impurity diffusion region (20) is formed at a predetermined distance from said first and second channel base regions (14a, 14b) and that said semiconductor device further comprises a gate oxide film of a MOSFET formed on said low impurity concentration epitaxial layer (12) between a channel base region (14a) and impurity diffusion region (20), a gate electrode formed on said gate oxide film, an insulation film formed on said gate electrode, and a high impurity concentration source region of the first conductivity type of said MOSFET formed in said first channel base region (14a).

Claim 8

The semiconductor device according to claim 2, characterized in that said first channel base region (14a) and second conductivity impurity diffusion region (20) constituting said diode (D3) are contiguous to each other.

Claim 9

The semiconductor device according to claim 2, characterized in that said first channel base region (14a) and second conductivity type impurity diffusion region (20) constituting said diode (D3) are contiguous to each other and an insulation layer is formed on said low impurity concentration epitaxial layer (12) between said channel base region (14a) and impurity diffusion region (20).

Claim 10

The semiconductor device according to claim 2, characterized in that the impurity concentration of said second conductivity type impurity diffusion region (20) constituting said diode (D3) is higher than the impurity concentration of said first and second channel base regions (14a, 14b).

Claim 11

The semiconductor device according to claim 2, characterized in that said gate electrode (17, 27) is formed in a V-shaped groove formed in said low impurity concentration epitaxial layer (12, 22).

Claim 12

The semiconductor device according to claim 2, characterized in that a lifetime killer is selectively diffused in said impurity diffusion region (20) constituting said diode (D3) and a surrounding portion of said low impurity concentration silicon epitaxial layer (12).