Patent US5128558A successfully refreshed from Google Patents.
US5128558A
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High speed, low power consumption voltage switching circuit for logic arrays
Assignee: Texas Instruments Inc
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Filing: 1991-05-21
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Granted: 1992-07-07
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Expires: 2011-05-21
Abstract
Abstract A memory device (10) includes switching circuitry 22 comprising sensing and control circuits (24 and 26) to predict the next state of the output of memory device (12) and to turn on and off current sources (20) responsive to said memory output to provide faster output transitions.
Inventors
- 👤 Kevin M. Ovens
- 👤 Jeffrey A. Niehaus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0175; H03K19/018; H03K19/01806; H03K19/01812; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
121 words
Circuitry for providing rapid switching of a logic array comprising a plurality of product lines and an output operable to generate high and low array output logic states, comprising: current generating circuitry coupled to said product lines and operable to generate a first and a second nonzero magnitude of current through said product lines, said current generating circuitry comprising: a diode having an anode coupled to control circuitry and a cathode coupled to ground, said diode operable to establish a voltage level; a plurality of transistors operable to generate current responsive to said voltage level; and said control circuitry operable to select which of said first and second nonzero magnitude of current is generated responsive to said array output logic state.
Claim 2
Dependent Claim
121 words
Circuitry for providing rapid switching of a logic array comprising a plurality of product lines and an output operable to generate high and low array output logic states, comprising: current generating circuitry coupled to said product lines and operable to generate a first and a second nonzero magnitude of current through said product lines, said current generating circuitry comprising: a diode having an anode coupled to control circuitry and a cathode coupled to ground, said diode operable to establish a voltage level; a plurality of transistors operable to generate current responsive to said voltage level; and said control circuitry operable to select which of said first and second nonzero magnitude of current is generated responsive to said array output logic state.
Claim 3
Dependent Claim
61 words
The circuitry of claim 1 wherein said control circuitry comprises circuitry coupled to said current generating circuitry operable to increase current generated by said current generating circuitry to said first magnitude responsive to a first array output logic state and to decrease current generated by said current generating circuitry to said second magnitude responsive to a second array output logic state.
Claim 4
Dependent Claim
48 words
The circuitry of claim 1 wherein said control circuitry comprises: sensing circuitry coupled to said array output and operable to detect the state of said array output; and switching control circuitry coupled to said sensing circuitry and operable to control the current generated by said current generating circuitry.
Claim 5
Dependent Claim
24 words
The circuitry of claim 3 wherein said sensing circuitry comprises a differential transistor pair coupled between said array output and said switching control circuitry.
Claim 6
Dependent Claim
71 words
The circuitry of claim 4 wherein said differential transistor pair comprises: a first NPN sensing transistor having an emitter coupled to a current source, a base coupled to said array output and a collector coupled to said switching control circuitry; and a second NPN sensing transistor having an emitter coupled to said current generating circuitry, a base coupled to a reference voltage, and a collector coupled to said switching control circuitry.
Claim 7
Dependent Claim
49 words
The circuitry of claim 5 wherein said sensing circuitry further comprises a first resistor coupled between said collector of said first NPN sensing transistor and a voltage source V s , and a second resistor coupled between said collector of said second NPN sensing transistor and V s .
Claim 8
Dependent Claim
78 words
The circuitry of claim 3 wherein said sensing circuitry comprises: a first NPN sensing transistor having an emitter coupled to said current generating circuitry, a base coupled to said collector of said second NPN sensing transistor, and a collector coupled to V cc ; and a second NPN sensing transistor having an emitter coupled to said array output, a base coupled to said collector of said first NPN sensing transistor, and a collector coupled to V cc .
Claim 9
Dependent Claim
54 words
The circuitry of claim 7 wherein said switching control circuitry further comprises: a first resistor coupled between said emitter of said first NPN sensing transistor and said anode of said diode of said current generating circuitry; and a second resistor coupled between said emitter of said second NPN sensing transistor and said array output.
Claim 10
Independent Claim
119 words
A method for providing rapid switching of a logic array comprising a plurality of product lines and an output operable to generate high and low logic states, comprising the steps of: sensing the logic state of said array output; and controlling a current through said product lines by selecting one of a first and a second nonzero magnitude of said current to be generated through said product lines responsive to said sensed state, whereby said logic state is sensed by a diode operatively coupled to said array output, and said one of a first and a second nonzero magnitude of said current is selected by a plurality of transistors operable to generate current responsive to said sensed logic state.
Claim 11
Independent Claim
119 words
A method for providing rapid switching of a logic array comprising a plurality of product lines and an output operable to generate high and low logic states, comprising the steps of: sensing the logic state of said array output; and controlling a current through said product lines by selecting one of a first and a second nonzero magnitude of said current to be generated through said product lines responsive to said sensed state, whereby said logic state is sensed by a diode operatively coupled to said array output, and said one of a first and a second nonzero magnitude of said current is selected by a plurality of transistors operable to generate current responsive to said sensed logic state.
Claim 12
Dependent Claim
21 words
The method of claim 9 wherein said controlling step comprises the step of controlling a current source with a switching transistor.
Claim 13
Dependent Claim
56 words
The method of claim 9 wherein said controlling step comprises the steps of: increasing said current through said product lines to said first magnitude when said array output is in a first logic state; and decreasing said current through said product lines to said second magnitude when said array output is in a second logic state.
Claim 14
Dependent Claim
24 words
The method of claim 11 and further comprising the step of increasing the voltage of said product lines responsive to said second logic state.
Claim 15
Dependent Claim
30 words
The method of claim 12 wherein said increasing the voltage step comprises the step of switching high a switching transistor coupled to said product liens and to a voltage source.
Claim 16
Dependent Claim
26 words
The method of claim 11 wherein said first logic state comprises a high logic state and wherein said second logic state comprises a low logic state.
Claim 17
Dependent Claim
23 words
The method of claim 9 wherein said sensing step comprises the step of comparing said array output state to a fixed reference voltage.
Claim 18
Dependent Claim
92 words
The method of claim 15 wherein said comparing step comprises the steps of: driving a first sensing transistor of a differential pair with said array output; driving a second sensing transistor of said differential pair with a reference voltage such that said first sensing transistor is turned off and said second sensing transistor is turned on when said array output is in a high logic state and said first sensing transistor is turned on and said second sensing transistor is turned off when said array output is in a low logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |