LSI array having power down capability

Claim 2

An integrated circuit device formed on a semiconductor chip, comprising: a plurality of pads; a first plurality of cells, each of said cells coupled to at least one of said plurality of pads; a second plurality of cells, each of said cells coupled to at least one of said plurality of pads, each of said cells comprising a plurality of first semiconductor devices interconnected to form a logic circuit; and first means comprising second semiconductor devices within each of said first plurality of cells, said first means coupled to different groups of said second plurality of cells for selectively enabling at least one of said different groups of said second plurality of cells, wherein substantially no current flows in the unselected groups of cells.

Claim 3

The integrated circuit device according to claim 1 wherein said first means comprises: second means for supplying a first voltage; a power down circuit comprising said second semiconductor devices within each of said first plurality of cells and coupled to said second means for receiving said first voltage and for selectively providing a second voltage substantially equal to said first voltage to at least one of said groups of said second plurality of cells.

Claim 4

The integrated circuit device according to claim 2 wherein said power down circuit comprises: a first supply voltage terminal coupled to a first of said plurality of pads; a second supply voltage terminal coupled to a second of said plurality of pads; third means coupled between said first and second supply voltage terminals and to a third of said plurality of pads for providing a logic signal in response to an input signal applied to said third pad; fourth means coupled between said first and second supply voltage terminals and coupled to said second means for receiving said first voltage and providing a regulated bias voltage based on said first voltage; and fifth means coupled between said first and second supply voltage terminals and coupled to said third and fourth means for providing said second voltage in response to said logic signal, said fifth means being biased by said regulated bias voltage.

Claim 5

The integrated circuit device according to claim 3 wherein said fourth means comprises: sixth means for providing a resistance; seventh means for providing a resistance; eighth means for providing a resistance; ninth means for providing a resistance; a first transistor having a base coupled to said second means for receiving said first voltage, an emitter coupled to said second supply voltage terminal by said sixth means, and a collector coupled to said first supply voltage terminal by said seventh means; a second transistor having a base coupled to said collector of said first transistor, a collector coupled to said first supply voltage terminal, and an emitter; and a third transistor having an emitter coupled to said second supply voltage terminal by said eighth means, and a base and collector coupled to said emitter of said second transistor by said ninth means and to said fifth means.

Claim 6

The integrated circuit device according to claim 4 wherein said fifth means comprises: tenth means for providing a resistance; eleventh means for providing a resistance; twelfth means for providing a resistance; a fourth transistor having a base coupled to said third means for receiving said logic signal, a collector coupled to said first supply voltage terminal, and an emitter; a fifth transistor having a base coupled to said base and collector of said third transistor, an emitter coupled to said second supply voltage terminal by said tenth means, and a collector coupled to said emitter of said fourth transistor by said eleventh means; and a sixth transistor having a base coupled to said collector of said fifth transistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second supply voltage terminal by said twelfth means for providing said second voltage.

Claim 7

The integrated circuit device according to claim 5 wherein said third means comprises: thirteenth means for providing a resistance; fourteenth means for providing a resistance; a seventh transistor having a base coupled to said third pad, a collector coupled to said first supply voltage terminal by said thirteenth means, and an emitter; an eighth transistor having a base coupled for receiving a reference voltage, a collector coupled to said first supply voltage terminal by said thirteenth means, and an emitter coupled to said emitter of said seventh transistor, wherein said collector of one of said seventh and eighth transistors is coupled to said base of said fourth transistor; and a ninth transistor having a base coupled to said second means for receiving said first voltage, a collector coupled to said emitters of said seventh and eighth transistors, and an emitter coupled to said second supply voltage terminal by said fourteenth means.

Claim 8

The integrated circuit device according to claim 6 wherein said third means further comprises fifteenth means for providing a resistance coupled between said collector of said seventh transistor and said thirteenth means.

Claim 9

A large scale integrated array comprising: a plurality of cells, including first and second portions, arranged in a matrix of rows and columns, each of said first portion of plurality of cells comprising a plurality of first semiconductor devices interconnected to form a circuit; a plurality of pads; a plurality of first means, each for supplying a first voltage; at least one second means comprising second semiconductor devices, each of said second means located within one of said cells of said second portion of plurality of cells and coupled to at least one of said plurality of pads and between one of said first means and a group of said cells of said first portion of plurality of cells for receiving said first voltage and selectively supplying a second voltage substantially similar to said first voltage to said group of said first portion of plurality of cells, for selectively enabling said group of said first portion of plurality of cells.

Claim 10

A large scale integrated array comprising: a plurality of cells, including first and second portions, arranged in a matrix of rows and columns, each of said first portion of plurality of cells comprising a plurality of first semiconductor devices interconnected to form a circuit; a plurality of pads; a plurality of first means, each for supplying a first voltage; at least one second means comprising second semiconductor devices, each of said second means located within one of said cells of said second portion of plurality of cells and coupled to at least one of said plurality of pads and between one of said first means and a group of said cells of said first portion of plurality of cells for receiving said first voltage and selectively supplying a second voltage substantially similar to said first voltage to said group of said first portion of plurality of cells, for selectively enabling said group of said first portion of plurality of cells.

Claim 11

The large scale integrated array according to claim 8 wherein said second means comprises: a first supply voltage terminal coupled to a first of said plurality of pads; a second supply voltage terminal coupled to a second of said plurality of pads; third means coupled between said first and second supply voltage terminals and to a third of said plurality of pads for providing a logic signal in response to an input signal applied to said third pad; fourth means coupled between said first and second supply voltage terminals and coupled to one of said first means for receiving said first voltage and providing a regulated bias voltage based on said first voltage; and fifth means coupled between said first and second supply voltage terminals and coupled to said third and fourth means for providing said second voltage in response to said logic signal, said fifth means being biased by said regulated bias voltage.

Claim 12

The large scale integrated array according to claim 9 wherein said fourth means comprises: sixth means for providing a resistance; seventh means for providing a resistance; eighth means for providing a resistance; ninth means for providing a resistance; a first transistor having a base coupled to said first means for receiving said first voltage, an emitter coupled to said second supply voltage terminal by said sixth means, and a collector coupled to said first supply voltage terminal by said seventh means; a second transistor having a base coupled to said collector of said first transistor, a collector coupled to said first supply voltage terminal, and an emitter; and a third transistor having an emitter coupled to said second supply voltage terminal by said eighth means, and a base and collector coupled to said emitter of said second transistor by said ninth means and to said fifth means.

Claim 13

The large scale integrated array according to claim 10 wherein said fifth means comprises: tenth means for providing a resistance; eleventh means for providing a resistance; twelfth means for providing a resistance; a fourth transistor having a base coupled to said third means for receiving said logic signal, a collector coupled to said first supply voltage terminal, and an emitter; a fifth transistor having a base coupled to said base and collector of said third transistor, an emitter coupled to said second supply voltage terminal by said tenth means, and a collector coupled to said emitter of said fourth transistor by said eleventh means; and a sixth transistor having a base coupled to said collector of said fifth transistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second supply voltage terminal by said twelfth means for providing said second voltage.

Claim 14

The large scale integrated array according to claim 11 wherein said third means comprises: thirteenth means for providing a resistance; fourteenth means for providing a resistance; a seventh transistor having a base coupled to said third pad, a collector coupled to said first supply voltage terminal by said thirteenth means, and an emitter; an eighth transistor having a base coupled for receiving a reference voltage, a collector coupled to said first supply voltage terminal by said thirteenth means, and an emitter coupled to said emitter of said seventh transistor, wherein said collector of one of said seventh and eighth transistors is coupled to said base of said fourth transistor; and a ninth transistor having a base coupled to said first means for receiving said first voltage, a collector coupled to said emitters of said seventh and eighth transistors, and an emitter coupled to said second supply voltage terminal by said fourteenth means.

Claim 15

The large scale integrated array according to claim 12 wherein said third means further comprises fifteenth means for providing a resistance coupled between said collector of said seventh transistor and said thirteenth means.

Claim 16

An improved monolithically integrated array having a plurality of pads , a plurality of cells including a first portion and a second portion, each of said cells including a first and second plurality of semiconductor devices, respectively, a plurality of regulators, each of said regulators supplying a first current source voltage to said first portion of said cells, wherein the improvement comprises: a plurality of metallization patterns including a first pattern and a second pattern, each of said first patterns coupled between one of said plurality of regulators and said first portion of said plurality of cells for conducting said first current source voltage; and at least one first means comprising said first plurality of semiconductor devices, each of said first means located within one of said first portion of plurality of cells and coupled by said first pattern to one of said regulators for receiving said first current source voltage and coupled to at least one cell in said second portion by said second pattern for selectively supplying a second current source voltage substantially similar to said first current source voltage to said at least one cell, wherein said at least one cell will be disabled when said second current source voltage is removed and substantially no current will flow in said cell.

Claim 17

An improved monolithically integrated array having a plurality of pads , a plurality of cells including a first portion and a second portion, each of said cells including a first and second plurality of semiconductor devices, respectively, a plurality of regulators, each of said regulators supplying a first current source voltage to said first portion of said cells, wherein the improvement comprises: a plurality of metallization patterns including a first pattern and a second pattern, each of said first patterns coupled between one of said plurality of regulators and said first portion of said plurality of cells for conducting said first current source voltage; and at least one first means comprising said first plurality of semiconductor devices, each of said first means located within one of said first portion of plurality of cells and coupled by said first pattern to one of said regulators for receiving said first current source voltage and coupled to at least one cell in said second portion by said second pattern for selectively supplying a second current source voltage substantially similar to said first current source voltage to said at least one cell, wherein said at least one cell will be disabled when said second current source voltage is removed and substantially no current will flow in said cell.

Claim 18

The monolithically integrated array according to claim 14 wherein said first means comprises: a first supply voltage terminal coupled to a first of said plurality of pads; a second supply voltage terminal coupled to a second of said plurality of pads; second means coupled between said first and second supply voltage terminals and to a third of said plurality of pads for providing an logic signal in response to an input signal applied to said third pad; third means coupled between said first and second supply voltage terminals and coupled to said first pattern for receiving said first current source voltage for providing a regulated bias voltage based on said first current source voltage; and fourth means coupled between said first and second supply voltage terminals and coupled to said second and third means for providing said second current source voltage in response to said logic signal, said fourth means being biased by said regulated bias voltage.

Claim 19

The monolithically integrated array according to claim 15 wherein said third means comprises: fifth means for providing a resistance; sixth means for providing a resistance; seventh means for providing a resistance; eighth means for providing a resistance; a first transistor having a base coupled to said first pattern for receiving said first current source voltage, an emitter coupled to said second supply voltage terminal by said fifth means, and a collector coupled to said first supply voltage terminal by said sixth means; a second transistor having a base coupled to said collector of said first transistor, a collector coupled to said first supply voltage terminal, and an emitter; and a third transistor having an emitter coupled to said second supply voltage terminal by said seventh means, and a base and collector coupled to said emitter of said second transistor by said eighth means and to said fourth means.

Claim 20

The monolithically integrated array according to claim 16 wherein said fourth means comprises: ninth means for providing a resistance; tenth means for providing a resistance; eleventh means for providing a resistance; a fourth transistor having a base coupled to said second means for receiving said logic signal, a collector coupled to said first supply voltage terminal, and an emitter; a fifth transistor having a base coupled to said base and collector of said third transistor, an emitter coupled to said second supply voltage terminal by said ninth means, and a collector coupled to said emitter of said fourth transistor by said tenth means; and a sixth transistor having a base coupled to said collector of said fifth transistor, a collector coupled to said first supply voltage terminal, and an emitter coupled to said second supply voltage terminal by said eleventh means for providing said second voltage.

Claim 21

The monolithically integrated array according to claim 17 wherein said second means comprises: twelfth means for providing a resistance; thirteenth means for providing a resistance; a seventh transistor having a base coupled to said third pad, a collector coupled to said first supply voltage terminal by said twelfth means, and an emitter; an eighth transistor having a base coupled for receiving a reference voltage, a collector coupled to said first supply voltage terminal by said twelfth means, and an emitter coupled to said emitter of said seventh transistor, wherein said collector of one of said seventh and eighth transistors is coupled to said base of said fourth transistor; and a ninth transistor having a base coupled to said first pattern for receiving said first current source voltage, a collector coupled to said emitters of said seventh and eighth transistors, and an emitter coupled to said second supply voltage terminal by said thirteenth means.

Claim 22

The monolithically integrated array according to claim 18 wherein said third means further comprises fourteenth means for providing a resistance coupled between said collector of said seventh transistor and said twelfth means.