Non-dissipative memory system

Claim 2

A memory system for a low powered device and comprising: multiple input terminals for selectively supplying memory addressing signals; decoder means coupled to and deriving all power from said memory addressing signals, providing ones of a predetermined number of separate word accessing signals in response to predetermined combinations of said input memory addressing signals; a plurality of output terminals; and an array of memory cells coupled to the decoder means and each cell providing predetermined signals at each of the output terminals in response to a respective one of the word accessing signals.

Claim 3

A memory system in accordance with claim 1, wherein the decoder means comprises at least one group of transistor pairs, each pair of one group comprising a different combination of the two transistor types NPN and PNP, and each group of pairs coupled to a respective input terminal.

Claim 4

A memory system in accordance with claim 1, wherein each memory cell stores the bits of one binary word and comprises one section for each bit of the word.

Claim 5

A memory system in accordance with claim 3, wherein each element of each memory cell includes a circuit which may be made conductive in response to the respective word accessing signal.

Claim 6

A memory system in accordance with claim 4, wherein each said circuit includes means for preventing conduction in the circuit.

Claim 7

A memory system in accordance with claim 1 further including buffer/driver means coupled to said decoder means and enabled by the word accessing signals.

Claim 8

A memory system in accordance with claim 6 and wherein each memory cell includes a plurality of sections and each section includes a circuit which may be made conductive and field-programmable means for preventing conduction.

Claim 9

A memory system in accordance with claim 7, wherein each buffer/driver means comprises a transistor, and a received word accessing signal enables the transistor to conduct.

Claim 10

A memory system in accordance with claim 8, wherein each buffer/driver means includes a second transistor circuit coupled to provide additional current for programming the conduction preventing means.

Claim 11

A memory system in accordance with claim 6 wherein the buffer/driver means comprises a predetermined number of portions, each portion coupled to a power source and a corresponding memory cell and each portion coupled to receive one of the word accessing signals.

Claim 12

An n-word memory system for a low powered device and comprising: a decoder network having a first predetermined number of inputs, the first predetermined number being less than n, said terminals adapted for receiving memory addressing signals, said decoder network deriving all power required for operation from said memory addressing signals, and having n outputs for supplying word accessing signals in response to predetermined combinations of said memory addressing signals; n buffer/driver circuits, each coupled to one of the respective decoder network outputs for being enabled by a respective word accessing signal; and n memory cells, each coupled to one of the buffer/driver circuits for being accessed in response to the word accessing signal, and having a second predetermined number of outputs, the second number being the number of bits per word in the system.

Claim 13

An n-word memory system for a low powered device and comprising: a decoder network having a first predetermined number of inputs, the first predetermined number being less than n, said terminals adapted for receiving memory addressing signals, said decoder network deriving all power required for operation from said memory addressing signals, and having n outputs for supplying word accessing signals in response to predetermined combinations of said memory addressing signals; n buffer/driver circuits, each coupled to one of the respective decoder network outputs for being enabled by a respective word accessing signal; and n memory cells, each coupled to one of the buffer/driver circuits for being accessed in response to the word accessing signal, and having a second predetermined number of outputs, the second number being the number of bits per word in the system.

Claim 14

A logic decoding device comprising: a plurality of input terminals for receiving encoded input signals; decoding means coupled to said terminals, responsive to said input signals and deriving all power required for operation therefrom, for producing distinct output signals in response to each combination of said input signals; and a plurality of output terminals, distinct ones of which are activated by the presence of said input signals, whereby said decoding device draws power from and only during the presence of said encoded input signals and substantially zero power when not receiving said encoded signals.

Claim 15

A logic decoding device comprising: a plurality of input terminals for receiving encoded input signals; decoding means coupled to said terminals, responsive to said input signals and deriving all power required for operation therefrom, for producing distinct output signals in response to each combination of said input signals; and a plurality of output terminals, distinct ones of which are activated by the presence of said input signals, whereby said decoding device draws power from and only during the presence of said encoded input signals and substantially zero power when not receiving said encoded signals.

Claim 16

The logic decoding device of claim 12 wherein said decoding means includes means for activating, in response to said input signals, only a portion of said decoding means, whereby power is also conserved during said decoding.

Claim 17

A parallel binary to plural line logic decoding device comprising: N input terminals for receiving parallel binary encoded input signals, where N is an integer; decoding means coupled to said N terminals, responsive to said binary encoded input signals and deriving all power required for operation therefrom, for producing distinct output signals in response to each combination of said binary encoded input signals; and 2 N-1 output terminals, distinct ones of which are activated by the presence of said binary encoded input signals, whereby said decoding device draws power from and only during the presence of said binary encoded input signals and substantially zero power when not receiving said binary encoded input signals.

Claim 18

A parallel binary to plural line logic decoding device comprising: N input terminals for receiving parallel binary encoded input signals, where N is an integer; decoding means coupled to said N terminals, responsive to said binary encoded input signals and deriving all power required for operation therefrom, for producing distinct output signals in response to each combination of said binary encoded input signals; and 2 N-1 output terminals, distinct ones of which are activated by the presence of said binary encoded input signals, whereby said decoding device draws power from and only during the presence of said binary encoded input signals and substantially zero power when not receiving said binary encoded input signals.

Claim 19

The logic decoding device of claim 1 wherein said decoding means includes means for activating, in response to said input signals, only portions of said decoding means, whereby power is also conserved during said decoding.