Integrated circuit read only memory bit organized in coincident select structure

Claim 2

A bipolar read only memory comprising a first plurality of address lines, an orthogonally-oriented second plurality of address lines, a first plurality of transistors arranged in a plurality of orthogonally oriented rows and columns, each of said first plurality of transistors having a base, a collector and an emitter, the bases of the transistors in each row of said first Plurality of transistors being coupled in common to a different one of said first plurality of address lines, the collectors of said first plurality of transistors being connected in common to a source of supply voltage, the emitters of selected transistors in each column of said first plurality of transistors being coupled in common to a different one of said second plurality of address lines, a first address decoder circuit for energizing a selected one of said first plurality of address lines, said first address decoder circuit having a plurality of outputs, each of said first plurality of address lines being coupled to a different output of said first address decoder circuit, a second address decoder circuit for selecting one or more but less than all of said second plurality of address lines, said second address decoder circuit having a plurality of outputs, an output circuit, and a second plurality of transistors for detecting the presence or absence of current through each of said first plurality of transistors addressed by said selected one of said first plurality of address lines and said selected one or more of said second plurality of address lines, each of said second plurality of transistors having a base, a collector, and an emitter, the base of each of said second plurality of transistors being coupled to a different output of said second address decoder circuit, the collector of each of said second plurality of transistors being coupled to a different one of said second plurality of address lines, and the emitters of said second plurality of transistors being coupled in common to said output circuit.

Claim 3

A bipolar read only memory comprising a first plurality of address lines, an orthogonally oriented second plurality of address lines, a first plurality of transistors arranged in a plurality of orthogonally oriented rows and columns, each of said first plurality of transistors having a base, a collector, and an emitter, the bases of the transistors in each row of said first plurality of transistors being coupled in common to a different one of said first plurality of address lines, the collectors of said first plurality of transistors being connected in common to a source of supply voltage, the emitters of selected transistors in each column of said first plurality of transistors being coupled in common to a different one of said second plurality of address lines, a first address decoder circuit for energizing a selected one of said first plurality of address lines, said first address decoder circuit having a plurality of outputs, each of said first plurality of address lines being coupled to a different output of said first address decoder circuit, a second address decoder circuit for selecting one or more but less than all of said second plurality of address lines, said second address decoder circuit having a plurality of outputs, a plurality of output circuits, and a second plurality of transistors arranged in one or more groups, each of said second plurality of transistors having a base, a collector, and an emitter, the bases of said second plurality o transistors being coupled in common to a source of reference voltage, the collectors of the transistors in each group of said second plurality of transistors being coupled in common to a different one of said output circuits, the emitter of each of said second plurality of transistors being coupled to a different one of said second plurality of address lines, and the emitter of each transistor in each group of said second plurality of transistors also being coupled to a different output of said second address decoder circuit.

Claim 4

A bipolar read only memory comprising a first plurality of address lines, an orthogonally oriented second plurality of address lines, a first plurality of transistors arranged in a plurality of orthogonally oriented rows and columns, each of said first plurality of transistors having a base, a collector, and an emitter, the bases of the transistors in each row of said first plurality of transistors being coupled in common to a different one of said first plurality of address lines, the collectors of said first plurality of transistors being connected in common to a source of supply voltage, the emitters of selected transistors in each column of said first plurality of transistors being coupled in common to a different one of said second plurality of address lines, a first address decoder circuit for energizing a selected one of said first plurality of address lines, said first address decoder circuit having a plurality of outputs, each of said first plurality of address lines being coupled to a different output of said first address decoder circuit, a second address decoder circuit for selecting one or more but less than all of said second plurality of address lines, said second address decoder circuit having a plurality of outputs, a plurality of output circuits, and a second plurality of transistors arranged in one or more groups, each of said second plurality of transistors having a base, a collector, and an emitter, the bases of said second plurality o transistors being coupled in common to a source of reference voltage, the collectors of the transistors in each group of said second plurality of transistors being coupled in common to a different one of said output circuits, the emitter of each of said second plurality of transistors being coupled to a different one of said second plurality of address lines, and the emitter of each transistor in each group of said second plurality of transistors also being coupled to a different output of said second address decoder circuit.

Claim 5

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion strips serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit having a plurality of outputs, each of said plurality of base diffusion stripes being coupled to a different output of said first address decoder circuit, a second address decoder circuit having a plurality of outputs, an output circuit, and a second plurality of transistors formed in said chip, each of said second plurality of transistors having a base, a collector, and an emitter, the base of each of said second plurality of transistors being coupled to a different output of said second address decoder circuit, the collector of each of said second plurality of transistors being coupled to a different one of said plurality of metal lines, and the emitters of said second plurality of transistors being coupled in common to said output circuit.

Claim 6

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion strips serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit having a plurality of outputs, each of said plurality of base diffusion stripes being coupled to a different output of said first address decoder circuit, a second address decoder circuit having a plurality of outputs, an output circuit, and a second plurality of transistors formed in said chip, each of said second plurality of transistors having a base, a collector, and an emitter, the base of each of said second plurality of transistors being coupled to a different output of said second address decoder circuit, the collector of each of said second plurality of transistors being coupled to a different one of said plurality of metal lines, and the emitters of said second plurality of transistors being coupled in common to said output circuit.

Claim 7

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit having a plurality of outputs, each of said plurality of base diffusion stripes being coupled to a different output of said first address decoder circuit, a second address decoder circuit having a plurality of outputs, a plurality of output circuits, and a second plurality of transistors formed in said chip and arranged in one or more groups, each of said second plurality of transistors having a base, a collector, and an emitter, the bases of said second plurality of transistors being coupled in common to a source of reference voltage, the collectors of the transistors in each group of said second plurality of transistors being coupled in common to a different one of said output circuits, the emitter of each of said second plurality of transistors being coupled to a different one of said plurality of metal lines, and the emitter of each transistor in each group of said second plurality of transistors also being coupled to a different output of said second address decoder circUit.

Claim 8

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit having a plurality of outputs, each of said plurality of base diffusion stripes being coupled to a different output of said first address decoder circuit, a second address decoder circuit having a plurality of outputs, a plurality of output circuits, and a second plurality of transistors formed in said chip and arranged in one or more groups, each of said second plurality of transistors having a base, a collector, and an emitter, the bases of said second plurality of transistors being coupled in common to a source of reference voltage, the collectors of the transistors in each group of said second plurality of transistors being coupled in common to a different one of said output circuits, the emitter of each of said second plurality of transistors being coupled to a different one of said plurality of metal lines, and the emitter of each transistor in each group of said second plurality of transistors also being coupled to a different output of said second address decoder circUit.

Claim 9

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit coupled to said base diffusion stripes, a bit detector circuit and a second address decoder circuit coupled to said metal lines, and at least one output circuit coupled to said bit detector circuit, at least one of said first and second address decoder circuits, comprising a plurality of AND circuits, each of said AND circuits including a plurality of inputs, an output coupled to one of said first and second plurality of address lines, an input transistor having a base coupled to said output, a collector coupled to a source of supply voltage, and a plurality of separate emitters coupled to said inputs, and an output emitter follower transistor having a collector connected to a source of supply voltage, a base coupled to the collector of said input transistor, and an emitter coupled to said output.

Claim 10

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit coupled to said base diffusion stripes, a bit detector circuit and a second address decoder circuit coupled to said metal lines, and at least one output circuit coupled to said bit detector circuit, at least one of said first and second address decoder circuits, comprising a plurality of AND circuits, each of said AND circuits including a plurality of inputs, an output coupled to one of said first and second plurality of address lines, an input transistor having a base coupled to said output, a collector coupled to a source of supply voltage, and a plurality of separate emitters coupled to said inputs, and an output emitter follower transistor having a collector connected to a source of supply voltage, a base coupled to the collector of said input transistor, and an emitter coupled to said output.

Claim 11

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit coupled to said base diffusion stripes, a bit detector circuit and a second address decoder circuit coupled to said metal lines, at least one output circuit coupled to said bit detector circuit, and a plurality of inverter circuits, each of said inverter circuits including an input, an output coupled to one of said first and second address decoder circuits, first and second transistors, each of said first and second transistors having a base, a collector, and an emitter, the base of said first transistor being coupled by a fiRst circuit to said input, the collector of said first transistor being coupled in common with the emitter of said second transistor to said output, the emitter of said first transistor being coupled to a source of reference voltage, the collector of said second transistor being coupled to a source of supply voltage, and control means coupled to said input and to the base of said second transistor, said control means being responsive to a change in state of an input signal applied to said input for turning said second transistor off before said first transistor is turned on.

Claim 12

A bipolar read only memory comprising a semiconductor chip, a first plurality of transistors arranged in said chip in a plurality of orthogonally oriented rows and columns, an isolation well formed in said chip and serving as a common collector for said first plurality of transistors, a plurality of spaced-apart base diffusion stripes formed in and extending across said isolation well in one direction, each of said base diffusion stripes serving as a common base for a different row of said first plurality of transistors, a plurality of emitter diffusion regions formed in and spaced apart along each of said base diffusion stripes, each of said emitter diffusion regions serving as the emitter of a different one of said first plurality of transistors, a plurality of spaced-apart metal lines extending orthogonal to said base diffusion stripes, each of said metal lines overlying a different one of the emitter diffusion regions in each of said base diffusion stripes, said metal lines being insulated from said base diffusion stripes and emitter diffusion regions and being connected to selected ones of said emitter diffusion regions through openings in the insulation between the metal lines and the emitter diffusion regions at selected locations where the metal lines overlie the emitter diffusion regions, a first address decoder circuit coupled to said base diffusion stripes, a bit detector circuit and a second address decoder circuit coupled to said metal lines, at least one output circuit coupled to said bit detector circuit, and a plurality of inverter circuits, each of said inverter circuits including an input, an output coupled to one of said first and second address decoder circuits, first and second transistors, each of said first and second transistors having a base, a collector, and an emitter, the base of said first transistor being coupled by a fiRst circuit to said input, the collector of said first transistor being coupled in common with the emitter of said second transistor to said output, the emitter of said first transistor being coupled to a source of reference voltage, the collector of said second transistor being coupled to a source of supply voltage, and control means coupled to said input and to the base of said second transistor, said control means being responsive to a change in state of an input signal applied to said input for turning said second transistor off before said first transistor is turned on.

Claim 13

A read only memory as in claim 6 wherein said control means comprises a third transistor having a base, a collector, and an emitter, the base of said third transistor being coupled by a second circuit to said input, the collector of said third transistor being coupled to the base of said second transistor, the emitter of said third transistor being coupled to a source of reference voltage, said second circuit and said third transistor operating to turn said second transistor off before said first circuit operates to turn said first transistor on and operating to turn said second transistor on after said first circuit operates to turn said first transistor off.