High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs

Claim 1

In a logic simulator for simulating a plurality of simulated logic devices, each said simulated logic device having at least one input and at least one output, said logic simulator including logic evaluator means; said simulator including: stimulus processor means for controlling logic states of inputs of said simulated logic devices when said simulated logic device inputs are not connected to other of said simulated logic device outputs, said stimulus processor means including: a plurality of independent event channels, each of said event channels being driven by an independent stimulus program containing one or more instruction sequences; program memory means for storing one or more of said instruction sequences of said stimulus programs, means for interpreting said stored instruction sequences to produce a sequence of input logic states, and means for supplying said sequence of input logic states from said interpreting means to said logic evaluator means to cause said logic evaluator means to respond to said sequence of input logic states produced by said interpreting means, said response of said logic evaluator means to any given sequence of input logic states occurring essentially concurrently with the production of said given sequence of input logic states by said stimulus processor means.