← Back to Patent Explorer
US5126920A Expired / Lapsed US ⏱️ 0.0 years remaining

Multiple integrated circuit interconnection arrangement

Assignee: Samsung Electronics Co Ltd
•
Filing: 1991-09-23
•
Granted: 1992-06-30
•
Expires: 2011-09-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A flexible chip interconnection includes a flexible film having interconnection lines formed on opposite sides thereof, with selected of the interconnection lines from one side connected by through-film conductors to interconnection lines on the other side. Insulating layers cover both sets of interconnection lines. Multi-chip circuits can be formed on the film with the interconnection lines directly connecting the chips.

Inventors

  • 👤 Vahram S. Cardashian
  • 👤 Jerald M. Loy

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 21:44
CPC Classifications
H; H05; H05K; H05K1/00; H05K1/02; H05K1/0286; H05K1/0287; H05K1/0289; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/688; H05K1/18; H05K1/189

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 289 words
A self-contained integrated circuit interconnect package adapted to be incorporated into an electrical or electromechanical device, wherein the device includes a printed wiring board with circuit connecting means for connecting to said package, comprising: a flexible, thin electrical insulating film, having first and second openings therethrough, and having first and second oppositely disposed surfaces; a first set of electrical interconnection lines, located on said first surface and including first and second integrated circuit connection sites; a second set of electrical interconnection lines located on said second surface; first and second electrical insulating layers covering said first and second surfaces, respectively, except at selected contact locations; first and second integrated circuits, wherein said first integrated circuit is connected to said first integrated circuit connection cite by wire bonds, and said second integrated circuit is connected to said second integrated circuit site by wire bonds; a set of interconnections for external circuits on said second surface, wherein some of said interconnections for external circuits are electrically connected to at least one of said first set of electrical interconnection lines or to at least one of said second set of electrical interconnection lines; first and second electrical connection through-films, located respectively in said first and second openings, wherein said through-films connect at least one of said first set of electrical interconnections which is connected to said first site to at least one of said second set of electrical interconnections which is connected to said second site, by way of at least one said second set of electrical interconnection lines, to thereby provide an electrical signal path between said intergrated circuit connection sites; and wherein some of said interconnections for external circuits are adapted to be directly connected to the circuit connecting means.
Claim 2
Dependent Claim 289 words
A self-contained integrated circuit interconnect package adapted to be incorporated into an electrical or electromechanical device, wherein the device includes a printed wiring board with circuit connecting means for connecting to said package, comprising: a flexible, thin electrical insulating film, having first and second openings therethrough, and having first and second oppositely disposed surfaces; a first set of electrical interconnection lines, located on said first surface and including first and second integrated circuit connection sites; a second set of electrical interconnection lines located on said second surface; first and second electrical insulating layers covering said first and second surfaces, respectively, except at selected contact locations; first and second integrated circuits, wherein said first integrated circuit is connected to said first integrated circuit connection cite by wire bonds, and said second integrated circuit is connected to said second integrated circuit site by wire bonds; a set of interconnections for external circuits on said second surface, wherein some of said interconnections for external circuits are electrically connected to at least one of said first set of electrical interconnection lines or to at least one of said second set of electrical interconnection lines; first and second electrical connection through-films, located respectively in said first and second openings, wherein said through-films connect at least one of said first set of electrical interconnections which is connected to said first site to at least one of said second set of electrical interconnections which is connected to said second site, by way of at least one said second set of electrical interconnection lines, to thereby provide an electrical signal path between said intergrated circuit connection sites; and wherein some of said interconnections for external circuits are adapted to be directly connected to the circuit connecting means.
Claim 3
Dependent Claim 14 words
The package of claim 1 wherein said wire bonds are formed by thermo-compression bonding.
Claim 4
Dependent Claim 14 words
The package of claim 1 wherein said wire bonds are formed by ultrasonic bonding.
Claim 5
Dependent Claim 35 words
The package of claim 1 wherein the majority of said interconnection lines are no more than 2 mils wide, and some of said interconnection lines are spaced as close as 2 mils, edge to edge.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-06-30 1995-12-30 1996-06-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-06-30 1999-12-30 2000-06-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-06-30 2003-12-30 2004-06-30 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag