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US5124270A Expired / Lapsed US ⏱️ 0.0 years remaining

Bipolar transistor having external base region

Assignee: Toshiba Corp
•
Filing: 1990-09-17
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Granted: 1992-06-23
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Expires: 2010-09-17
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Abstract

Abstract A bipolar transistor is provided with an external base region. The bipolar transistor comprises a first semiconductor layer of a first conductivity type, the first semiconductor layer serving as a collector region, a second semiconductor layer of a second conductivity type, which is formed on the first semiconductor layer and includes a base region and an external base region located around the base region, a third semiconductor layer of the first conductivity type, which is formed on the second semiconductor layer and serves as an emitter region, a metal layer formed on the third semiconductor layer and serving as an emitter electrode, the metal layer including a first metal layer portion which is substantially as wide as the base region located in an intrinsic transistor region, and a second metal layer portion which is formed on the first metal layer portion and is wider than the first metal portion, a base electrode located on the external base region of the second semiconductor layer, and a collector electrode connected to the first semiconductor layer.

Inventors

  • 👤 Kouhei Morizuka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:15
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/072

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 166 words
A method for manufacturing a bipolar transistor having an external base region, said method comprising the steps of: forming a first semiconductor layer of a first conductivity type on a semiconductor substrate, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of the first conductivity type on the second semiconductor layer; stacking first and second metal layers over the third semiconductor layer; selectively etching the second metal layer, to thereby form a second metal layer pattern; selectively side-etching the first metal layer to a predetermined extent, using the second metal layer pattern as a mask, to thereby form a first metal layer pattern which is more side-etched than the second metal layer pattern; selectively etching the third semiconductor layer, using the first metal layer pattern as a mask, to thereby expose the second semiconductor layer; and forming a metal layer connected to the second semiconductor layer, by using the second metal layer pattern as a mask.
Claim 2
Independent Claim 166 words
A method for manufacturing a bipolar transistor having an external base region, said method comprising the steps of: forming a first semiconductor layer of a first conductivity type on a semiconductor substrate, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of the first conductivity type on the second semiconductor layer; stacking first and second metal layers over the third semiconductor layer; selectively etching the second metal layer, to thereby form a second metal layer pattern; selectively side-etching the first metal layer to a predetermined extent, using the second metal layer pattern as a mask, to thereby form a first metal layer pattern which is more side-etched than the second metal layer pattern; selectively etching the third semiconductor layer, using the first metal layer pattern as a mask, to thereby expose the second semiconductor layer; and forming a metal layer connected to the second semiconductor layer, by using the second metal layer pattern as a mask.
Claim 3
Dependent Claim 14 words
A method according to claim 1, wherein the third semiconductor layer is etched isotropically.
Claim 4
Dependent Claim 42 words
A method according to claim 1, further comprising the step of injecting ions to part of the first semiconductor layer, by using both the first and second metal layer patterns as a mask, whereby the part is made to have high resistance.

References Cited (Backward Citations)

US4599791A Cited
JPS61131480A Cited
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JPS61187364A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-06-23 1995-12-23 1996-06-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-06-23 1999-12-23 2000-06-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-06-23 2003-12-23 2004-06-23 $7700.00 Window Closed / Lapsed

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