Semiconductor integrated circuit device

Claim 1

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates and a second macro cell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical macro cells included in a prepared logical cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and wherein the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second macro cell in said first path.

Claim 2

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates and a second macro cell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical macro cells included in a prepared logical cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and wherein the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second macro cell in said first path.

Claim 4

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical polycells included in a prepared logical cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and the second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second polycell in said first path.

Claim 5

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical polycells included in a prepared logical cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and the second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment of the second polycell in said first path.

Claim 7

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates, a second macro cell including bipolar and CMOS gates, a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical macro cells and logical polycells including in a prepared logic cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and said second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment with the second macro cell and the second polycell in said first path.

Claim 8

A method of manufacturing a standard cell semiconductor integrated circuit device incorporating a first macro cell including CMOS gates without bipolar gates, a second macro cell including bipolar and CMOS gates, a first polycell including CMOS gates without bipolar gates and a second polycell including bipolar and CMOS gates comprising: a function design step; a logic design step where a desired logic according to said function design step is assembled using logical macro cells and logical polycells including in a prepared logic cell library; evaluating a plurality of paths for said semiconductor integrated circuit device, and determining at least a first path which has a delay time greater than a predetermined delay time specification; allotting physical cells to the logical macro cells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first macro cell and the second macro cell are prepared, wherein the first macro cell is allotted in areas of said integrated circuit other than said first path and the second macro cell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; allotting physical cells to the logical polycells with reference to a physical cell library where a set of a plurality of physical cells having the same logic function including the first polycell and the second polycell are prepared, wherein the first polycell is allotted in areas of said integrated circuit other than said first path and said second polycell is allotted in a portion of the integrated circuit which defines said first path to reduce delay time along said first path; and returning to said logic design step when the predetermined delay time specification is not satisfied even by the allotment with the second macro cell and the second polycell in said first path.