EP0133131A2
Expired / Lapsed
EP
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Master slice IC device
Assignee: Fujitsu Ltd
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Filing: 1984-07-26
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Granted: —
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Expires: 2004-07-26
Abstract
Abstract A master slice IC device comprising at least two kind of basic cells (6,8); that is, a first kind of basic cells (6) each having one or more n-type MIS transistors (Q2) and one or more p-type MIS transistors (01) to form a CMIS logic circuit, and a second kind of basic cells (8) each comprising an npn-type bipolar transistor (Q3) and a pnp-type bipolar transistor (Q4) to form a bipolar buffer circuit having a large drive ability, The second kind of basic cells (8) are used, for example, only when the fan-out number is large and/or the length of the connection lines is long, thereby realizing a high degree of freedom in circuit design and a high operating speed without increasing the power consumption.
Inventors
- 👤 Tetsu Tanizawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-23 02:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/996
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
105 words
A master slice integrated circuit device comprising: a basic cell array portion disposed at an inner area of a semiconductor chip; and a plurality of input/output cells arranged at the periphery of said basic cell array portion and effecting signal transmission to and from external circuits; said basic cell array portion having a plurality of basic cell units disposed in an array, and each of said basic cell units comprising one or more first basic cells each having a p-type MIS transistor and an n-type MIS transistor and one or more second basic cells each having a pnp-type bipolar transistor and an npn-type bipolar transistor.
Claim 2
Dependent Claim
105 words
A master slice integrated circuit device comprising: a basic cell array portion disposed at an inner area of a semiconductor chip; and a plurality of input/output cells arranged at the periphery of said basic cell array portion and effecting signal transmission to and from external circuits; said basic cell array portion having a plurality of basic cell units disposed in an array, and each of said basic cell units comprising one or more first basic cells each having a p-type MIS transistor and an n-type MIS transistor and one or more second basic cells each having a pnp-type bipolar transistor and an npn-type bipolar transistor.
Claim 3
Dependent Claim
100 words
A master slice integrated circuit device according to claim 1, wherein each of said basic cell units comprises an n-type semiconductor region and a p-type semiconductor region formed adjacent to said n-type semiconductor region, on said n-type semiconductor region being formed an npn-type bipolar transistor and p-channel MIS transistors on both sides of said npn-type bipolar transistor, on said p-type semiconductor region being formed a pnp-type bipolar transistor and n-channel MIS transistors on both sides of said pnp-type bipolar transistor and adjacent to said p-channel MIS transistors, said p-channel MIS transistors and adjacent n-channel MIS transistors having common gate electrodes.
Claim 4
Dependent Claim
87 words
A master slice integrated circuit device according to claim 2, wherein each of said basic cell units comprises n-channel MIS control transistors having control gates between said pnp-type bipolar transistor and said n-channel MIS transistors and p-channel MIS control transistors having control gates between said npn-type bipolar transistor and said p-channel MIS transistors, the control gates of said n-channel MIS control transistors and the control gates of said p-channel MIS control transistors being separate from each other and being supplied with power supply voltages or signal voltages.
Claim 5
Dependent Claim
52 words
A master slice integrated circuit device according to claim 3, wherein each of said n-channel MIS control transistors and said p-channel MIS control transistors is formed by commonly using a base region of an adjacent bipolar transistor and a diffusion region of an adjacent MIS transistor as drain and source regions thereof.
Claim 6
Dependent Claim
33 words
A master slice integrated circuit device according to claim 1 or 2 or 3 or 4, wherein each of said pnp-type bipolar transistors and said npn-type bipolar transistors is a vertical type transistor.
Claim 7
Dependent Claim
112 words
A master slice integrated circuit device comprising: a basic cell array portion disposed at an inner area of a semiconductor chip; and a plurality of input/output cells arranged at the periphery of said basic cell array portion and effecting signal transmission to and from external circuits; said basic cell array portion having a plurality of first basic cells each comprising a p-type MIS transistor and an n-type MIS transistor and a plurality of second basic cells each comprising a pnp-type bipolar transistor and an npn-type bipolar transistor, and said second basic cells being disposed so that said second basic cells divide said plurality of first basic cells into a plurality of blocks.
Claim 8
Dependent Claim
112 words
A master slice integrated circuit device comprising: a basic cell array portion disposed at an inner area of a semiconductor chip; and a plurality of input/output cells arranged at the periphery of said basic cell array portion and effecting signal transmission to and from external circuits; said basic cell array portion having a plurality of first basic cells each comprising a p-type MIS transistor and an n-type MIS transistor and a plurality of second basic cells each comprising a pnp-type bipolar transistor and an npn-type bipolar transistor, and said second basic cells being disposed so that said second basic cells divide said plurality of first basic cells into a plurality of blocks.
Claim 9
Dependent Claim
51 words
A master slice integrated circuit device according to claim 6, wherein said p-type MIS transistor and said n-type MIS transistor of said first basic cell are used to form a CMIS logic circuit, and said pnp-type bipolar transistor and said npn-type bipolar transistor are used to form a bipolar buffer circuit.
References Cited (Backward Citations)
No citation records indexed.
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