Method of fabricating hemt device with selective etching of gallium arsenide antimonide

Claim 1

A method of manufacturing a semiconductor device comprising a field effect transistor, with a heterojunction formed therein and utilizing a two-dimensional electron gas established at said heterojunction, comprising the steps of: providing a first semiconductor layer of undoped indium gallium arsenide on a semi-insulating semiconductor substrate of indium phosphide as a channel layer in which the two-dimensional electron gas is generatable; providing a second semiconductor layer of n-type indium aluminum arsenide on said first semiconductor layer; providing a third semiconductor layer of n-type gallium arsenide antimonide on said second semiconductor layer; providing an ohmic electrode on said third semiconductor layer in correspondence to source and drain of the field effect transistor; applying a photoresist, having an opening exposing a part of said third semiconductor layer in correspondence to a gate of said field effect transistor, on said third semiconductor layer; carrying out an anisotropic etching process acting selectively upon said third semiconductor layer for providing a groove in said exposed part of the third semiconductor layer such that a part of said second semiconductor layer is exposed, said step of anisotropic etching stopping automatically upon exposure of said second semiconductor layer; and depositing a gate electrode by filling said groove with a conductive material.

Claim 2

A method of manufacturing a semiconductor device comprising a field effect transistor, with a heterojunction formed therein and utilizing a two-dimensional electron gas established at said heterojunction, comprising the steps of: providing a first semiconductor layer of undoped indium gallium arsenide on a semi-insulating semiconductor substrate of indium phosphide as a channel layer in which the two-dimensional electron gas is generatable; providing a second semiconductor layer of n-type indium aluminum arsenide on said first semiconductor layer; providing a third semiconductor layer of n-type gallium arsenide antimonide on said second semiconductor layer; providing an ohmic electrode on said third semiconductor layer in correspondence to source and drain of the field effect transistor; applying a photoresist, having an opening exposing a part of said third semiconductor layer in correspondence to a gate of said field effect transistor, on said third semiconductor layer; carrying out an anisotropic etching process acting selectively upon said third semiconductor layer for providing a groove in said exposed part of the third semiconductor layer such that a part of said second semiconductor layer is exposed, said step of anisotropic etching stopping automatically upon exposure of said second semiconductor layer; and depositing a gate electrode by filling said groove with a conductive material.

Claim 8

A method of manufacturing a semiconductor device comprising an enhancement-mode field effect transistor and a depletion-mode field effect transistor, with a heterojunction formed therein and utilizing a two-dimensional electron gas established at said heterojunction, comprising the steps of: providing a first semiconductor layer of undoped indium gallium arsenide on a semi-insulating semiconductor substrate of indium phosphide as a channel layer in which the two-dimensional electron gas is generatable; providing a second semiconductor layer of n-type indium aluminum arsenide as an electron-supply layer on said first semiconductor layer; providing a third semiconductor layer of n-type gallium arsenide on said second semiconductor layer; providing a fourth semiconductor layer of n-type indium aluminum arsenide on said third semiconductor layer; providing a fifth semiconductor layer of n-type gallium arsenide antimonide on said fourth semiconductor layer; providing ohmic electrodes on said fifth semiconductor layer in correspondence to source and drain of the enhancement-mode field effect transistor and the depletion-mode field effect transistor; applying a photoresist, having an opening exposing a first part of said fifth semiconductor layer in correspondence to a gate of said enhancement-mode field effect transistor, on said fifth semiconductor layer; carrying out a first etching process acting selectively upon said fifth semiconductor layer for providing a first groove in said exposed, first part of the fifth semiconductor layer such that a corresponding first part of said fourth semiconductor layer is exposed through said first groove, said first etching process stopping automatically upon exposure of said fourth semiconductor layer through said first groove; carrying out a second etching process for extending said first groove by removing said first part of the fourth semiconductor layer thereby to expose a corresponding part of the third semiconductor layer; forming another opening in said photoresist for exposing therethrough a second part of said fifth semiconductor layer in correspondence to a gate of said depletion-mode field effect transistor; carrying out a third etching process acting selectively upon said fifth and third semiconductor layers for providing a second groove in said exposed, second part of said fifth semiconductor layer such that a corresponding, second part of the fourth semiconductor layer is exposed through said second groove and for further extending said first groove so as to expose a corresponding part of the second semiconductor layer, said third etching process step acting upon said fifth semiconductor layer and stopping automatically upon exposure of said fourth semiconductor layer through said second groove and acting upon said third semiconductor layer and stopping automatically upon exposure of said second semiconductor layer through said first groove; and providing a first gate electrode and a second gate electrode by filling said first groove and second groove with a conductive material.

Claim 9

A method of manufacturing a semiconductor device comprising an enhancement-mode field effect transistor and a depletion-mode field effect transistor, with a heterojunction formed therein and utilizing a two-dimensional electron gas established at said heterojunction, comprising the steps of: providing a first semiconductor layer of undoped indium gallium arsenide on a semi-insulating semiconductor substrate of indium phosphide as a channel layer in which the two-dimensional electron gas is generatable; providing a second semiconductor layer of n-type indium aluminum arsenide as an electron-supply layer on said first semiconductor layer; providing a third semiconductor layer of n-type gallium arsenide on said second semiconductor layer; providing a fourth semiconductor layer of n-type indium aluminum arsenide on said third semiconductor layer; providing a fifth semiconductor layer of n-type gallium arsenide antimonide on said fourth semiconductor layer; providing ohmic electrodes on said fifth semiconductor layer in correspondence to source and drain of the enhancement-mode field effect transistor and the depletion-mode field effect transistor; applying a photoresist, having an opening exposing a first part of said fifth semiconductor layer in correspondence to a gate of said enhancement-mode field effect transistor, on said fifth semiconductor layer; carrying out a first etching process acting selectively upon said fifth semiconductor layer for providing a first groove in said exposed, first part of the fifth semiconductor layer such that a corresponding first part of said fourth semiconductor layer is exposed through said first groove, said first etching process stopping automatically upon exposure of said fourth semiconductor layer through said first groove; carrying out a second etching process for extending said first groove by removing said first part of the fourth semiconductor layer thereby to expose a corresponding part of the third semiconductor layer; forming another opening in said photoresist for exposing therethrough a second part of said fifth semiconductor layer in correspondence to a gate of said depletion-mode field effect transistor; carrying out a third etching process acting selectively upon said fifth and third semiconductor layers for providing a second groove in said exposed, second part of said fifth semiconductor layer such that a corresponding, second part of the fourth semiconductor layer is exposed through said second groove and for further extending said first groove so as to expose a corresponding part of the second semiconductor layer, said third etching process step acting upon said fifth semiconductor layer and stopping automatically upon exposure of said fourth semiconductor layer through said second groove and acting upon said third semiconductor layer and stopping automatically upon exposure of said second semiconductor layer through said first groove; and providing a first gate electrode and a second gate electrode by filling said first groove and second groove with a conductive material.

Claim 15

A method of manufacturing a semiconductor device comprising steps of: providing a second semiconductor layer of gallium arsenide antimonide on a first semiconductor layer containing indium; and selectively removing a part of said second semiconductor layer by an etching process using a chloride etching gas such that the first semiconductor layer is exposed through said part of the second semiconductor layer.

Claim 16

A method of manufacturing a semiconductor device comprising steps of: providing a second semiconductor layer of gallium arsenide antimonide on a first semiconductor layer containing indium; and selectively removing a part of said second semiconductor layer by an etching process using a chloride etching gas such that the first semiconductor layer is exposed through said part of the second semiconductor layer.