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US5117227A
Expired / Lapsed
US
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Continuously integrating high-resolution analog-to-digital converter
Assignee: Agilent Technologies Inc
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Filing: 1991-09-27
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Granted: 1992-05-26
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Expires: 2011-09-27
Abstract
Abstract A continuously integrating analog-to-digital converter (ADC) calculates a digital output by integrating an input voltage over a number of time intervals using a multisloping technique to define the input voltage in terms of a slope count. A residue ADC is used in lieu of a run-down interval of the integrator to calculate the least significant bits of the ADC digital output. This is accomplished by first sampling the integrator output voltage, and then after a number of time intervals, sampling the integrator output voltage a second tune. The difference between the two residue voltages is converted into a fractional slope count by multiplication with a calibration constant. The fractional slope count can then be added to the slope count from the integrator, so that the resulting total slope count is directly proportional to the input voltage at a high resolution. Multiplication by the calibration constant may be effectuated by controlling the gain on the residue ADC with a digital-to-analog converter (DAC), or like device.
Inventors
- 👤 Wayne C. Goeke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:15
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
144 words
A system for converting an input analog signal into an output digital signal, comprising: integrating means having an integrator configured to integrate said input analog signal combined with input reference signals, a comparator connected to said integrator configured to monitor polarity changes, and integrator logic connected to said comparator configured to control the application of said reference input signals and provide an integrator count; a residue ADC adapted to measure the integrated output at the beginning and end of a time interval to derive respective first and second residue voltages; and control logic connected to said integrating means and said residue ADC, said control logic configured to convert said first and second residue voltages into a residue count and configured to mathematically combine (1) said residue count, and (2) the integrator count within said time interval, so as to derive said output digital signal.
Claim 2
Independent Claim
144 words
A system for converting an input analog signal into an output digital signal, comprising: integrating means having an integrator configured to integrate said input analog signal combined with input reference signals, a comparator connected to said integrator configured to monitor polarity changes, and integrator logic connected to said comparator configured to control the application of said reference input signals and provide an integrator count; a residue ADC adapted to measure the integrated output at the beginning and end of a time interval to derive respective first and second residue voltages; and control logic connected to said integrating means and said residue ADC, said control logic configured to convert said first and second residue voltages into a residue count and configured to mathematically combine (1) said residue count, and (2) the integrator count within said time interval, so as to derive said output digital signal.
Claim 3
Dependent Claim
19 words
The system of claim 1, further comprising a means for mathematically multiplying said residue count by a calibration constant.
Claim 4
Dependent Claim
17 words
The system of claim 1, further comprising a means for controlling the gain on said residue ADC.
Claim 5
Dependent Claim
24 words
The system of claim 1, further comprising switching capacitors for providing said input analog signal and said reference input signals to said integrating means.
Claim 6
Dependent Claim
21 words
The system of claim 1, further comprising a sample and hold circuit connected between said integrating means and said residue ADC.
Claim 7
Independent Claim
84 words
A method of computing an output digital signal from an input analog signal, comprising the steps of: integrating said input analog signal combined with input reference signals; sampling a first integrated output voltage to commence a reading; counting said reference input reference signals; sampling a second integrated output voltage to terminate said reading; and computing said output digital signal by mathematically combining (1) the difference between said first and second integrated output voltages and (2) the count of input reference signals during said reading.
Claim 8
Independent Claim
84 words
A method of computing an output digital signal from an input analog signal, comprising the steps of: integrating said input analog signal combined with input reference signals; sampling a first integrated output voltage to commence a reading; counting said reference input reference signals; sampling a second integrated output voltage to terminate said reading; and computing said output digital signal by mathematically combining (1) the difference between said first and second integrated output voltages and (2) the count of input reference signals during said reading.
Claim 9
Dependent Claim
28 words
The method of claim 6, further comprising the step of commencing a second reading after a first reading has already been commenced, but not terminated, thereby overlapping readings.
Claim 10
Dependent Claim
29 words
The method of claim 6, further comprising the step of commencing and terminating a second reading after a first reading has been commenced but not terminated, thereby overlapping readings.
Claim 11
Dependent Claim
32 words
The method of claim 6, further comprising the step of combining said input reference signals with said input analog signal so as to maintain the integrated output voltage within predetermined signal limits.
Claim 12
Dependent Claim
50 words
The system of claim 6, further comprising the steps of: multiplying said difference between said first and second integrated output voltages by a calibration constant to derive a modified residue count; and adding said modified residue count to said count of input reference signals to derive said output digital signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |