Patent US5115151A successfully refreshed from Google Patents.
US5115151A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Triple comparator circuit
Assignee: Western Digital Corp
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Filing: 1990-06-08
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Granted: 1992-05-19
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Expires: 2010-06-08
Abstract
Abstract A comparator which is used to compare two analog voltages and provide a single ended output comprises three CMOS differential amplifiers. The use of three differential amplifiers provides improved matching of input capacitance, and a reduction in propagation delay over prior art use of a single differential amplifier. The comparator may be adopted for use in certain CMOS processes to extend the maximum operating voltage by limiting the internal node voltages otherwise subject to damage from impact ionization. An alternative embodiment is disclosed for comparing two analog voltages that are outside the power supply voltage range.
Inventors
- 👤 Richard W. Hull
- 👤 Timothy G. O'Shaughnessy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:00
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/2481; G; G01; G01R; G01R19/00; G01R19/0038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
138 words
A high impedance differential comparator circuit having symmetrical delay comprising; a first MOS differential amplifier having a first input, a second input and an output, the first input connected to a first signal source and the second input connected to second signal source; a second MOS differential amplifier identical to the first differential amplifier having the first input connected to the second signal source and the second input connected to the first signal source; a third MOS differential amplifier having a first input connected to the output of the first differential amplifier, a second input connected to the output of the second differential amplifier and an output; and, means for clamping the outputs of the first and second differential amplifiers thereby providing a maximum limit on voltage at the first and second inputs to the third differential amplifier.
Claim 2
Dependent Claim
138 words
A high impedance differential comparator circuit having symmetrical delay comprising; a first MOS differential amplifier having a first input, a second input and an output, the first input connected to a first signal source and the second input connected to second signal source; a second MOS differential amplifier identical to the first differential amplifier having the first input connected to the second signal source and the second input connected to the first signal source; a third MOS differential amplifier having a first input connected to the output of the first differential amplifier, a second input connected to the output of the second differential amplifier and an output; and, means for clamping the outputs of the first and second differential amplifiers thereby providing a maximum limit on voltage at the first and second inputs to the third differential amplifier.
Claim 3
Dependent Claim
180 words
A high impedance differential comparator circuit having symmetrical delay comprising: first and second current source biased MOS differential amplifiers with active current mirror loads, each amplifier having a first input, a second input, and an output, the first input of the first amplifier and the second input of the second amplifier connected to a first signal source and the second input of the first amplifier and the first input of the second amplifier connected to a second signal source; a third current source biased MOS differential amplifier having an active current mirror load and having a first input connected to the output of the first amplifier and a second input connected to the output of the second amplifier and an output; a first diode connected MOS device drain connected intermediate the output of the first amplifier and the first input of the third amplifier; a second diode connected MOS device drain connected intermediate the output of the second amplifier and the second input of the third amplifier; and, a MOS invertor stage connected to the output of the third amplifier.
Claim 4
Dependent Claim
180 words
A high impedance differential comparator circuit having symmetrical delay comprising: first and second current source biased MOS differential amplifiers with active current mirror loads, each amplifier having a first input, a second input, and an output, the first input of the first amplifier and the second input of the second amplifier connected to a first signal source and the second input of the first amplifier and the first input of the second amplifier connected to a second signal source; a third current source biased MOS differential amplifier having an active current mirror load and having a first input connected to the output of the first amplifier and a second input connected to the output of the second amplifier and an output; a first diode connected MOS device drain connected intermediate the output of the first amplifier and the first input of the third amplifier; a second diode connected MOS device drain connected intermediate the output of the second amplifier and the second input of the third amplifier; and, a MOS invertor stage connected to the output of the third amplifier.
Claim 5
Dependent Claim
33 words
A comparator circuit as defined in claim 2 further comprising means for biasing the current sources of the first and second amplifiers and means for biasing the current source of the third amplifier.
Claim 6
Dependent Claim
45 words
A differential comparator circuit as defined in claim 3 further comprising a first voltage supply connected to the current sources of the first and second amplifiers and a second voltage supply connected to the current source of the third amplifier and the MOS invertor stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |