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US5114869A
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Method for producing reverse staggered type silicon thin film transistor
Assignee: Seiko Precision Inc
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Filing: 1989-05-26
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Granted: 1992-05-19
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Expires: 2009-05-26
Abstract
Abstract A method for producing a reverse staggered type silicon thin film transistor includes the steps of forming a gate insulating layer on a substrate having a gate electrode, the gate insulating layer having a transistor-forming portion; forming an intrinsic silicon film on the transistor-forming portion of the gate insulating layer; forming an n-type silicon layer on the intrinsic silicon layer; forming a source electrode on the n-type silicon layer; forming a drain electrode on the n-type silicon layer; forming a resist layer on the source electrode and drain electrode and having the same shape thereof; subsequently removing a portion of the n-type silicon layer by using the resist layer as a mask, such that there remains a predetermined thickness of the n-type silicon layer; and doping the predetermined thickness of the n-type silicon layer with p-type impurities by using the resist layer as a mask.
Inventors
- 👤 Sakae Tanaka
- 👤 Yoshiaki Watanabe
- 👤 Katsuo Shirai
- 👤 Yoshihisa Ogiwara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
120 words
A method for producing a reverse staggered type silicon thin film transistor, comprising the steps of: forming a gate electrode on a surface of a substrate, and forming a gate insulating layer on said substrate and gate electrode; forming an intrinsic silicon film on a predetermined portion of the gate insulating layer overlying said gate electrode and extending beyond said gate electrode; forming an n-type silicon layer on said intrinsic silicon layer to cover said predetermined portion thereof; forming a source electrode and a drain electrode to overlie a first portion of said n-type silicon layer; and doping a second portion of said n-type silicon layer other than said first portion thereof with p-type impurities by means of a mask.
Claim 2
Independent Claim
120 words
A method for producing a reverse staggered type silicon thin film transistor, comprising the steps of: forming a gate electrode on a surface of a substrate, and forming a gate insulating layer on said substrate and gate electrode; forming an intrinsic silicon film on a predetermined portion of the gate insulating layer overlying said gate electrode and extending beyond said gate electrode; forming an n-type silicon layer on said intrinsic silicon layer to cover said predetermined portion thereof; forming a source electrode and a drain electrode to overlie a first portion of said n-type silicon layer; and doping a second portion of said n-type silicon layer other than said first portion thereof with p-type impurities by means of a mask.
Claim 3
Dependent Claim
26 words
A method according to claim 1; wherein said step of doping includes the step of using said source electrode and said drain electrode as the mask.
Claim 4
Dependent Claim
30 words
A method according to claim 1; wherein said step of doping includes the step of using a resist layer formed on said source electrode and drain electrode as the mask.
Claim 5
Dependent Claim
25 words
A method according to claim 1; wherein said step of doping includes the step of forming said doped n-type silicon layer into an intrinsic layer.
Claim 6
Dependent Claim
25 words
A method according to claim 1; wherein said step of doping includes the step of forming said doped n-type silicon layer into a p-type layer.
Claim 7
Independent Claim
149 words
A method for producing a reverse staggered type silicon thin film transistor, comprising the steps of: forming a gate electrode on a surface of a substrate, and forming a gate insulating layer on said substrate and gate electrode; forming an intrinsic silicon film on a predetermined portion of the gate insulating layer that overlays said gate electrode and extends beyond said gate electrode; forming an n-type silicon layer on said intrinsic silicon layer to cover said predetermined portion thereof; forming a source electrode and a drain electrode to overlie a first portion of said n-type silicon layer; subsequently removing a portion of said n-type silicon layer not covered by said source and drain electrodes by means of a mask, such that there remains a predetermined thickness of said n-type silicon layer; and doping said predetermined thickness of said n-type silicon layer with p-type impurities by means of a mask.
Claim 8
Independent Claim
149 words
A method for producing a reverse staggered type silicon thin film transistor, comprising the steps of: forming a gate electrode on a surface of a substrate, and forming a gate insulating layer on said substrate and gate electrode; forming an intrinsic silicon film on a predetermined portion of the gate insulating layer that overlays said gate electrode and extends beyond said gate electrode; forming an n-type silicon layer on said intrinsic silicon layer to cover said predetermined portion thereof; forming a source electrode and a drain electrode to overlie a first portion of said n-type silicon layer; subsequently removing a portion of said n-type silicon layer not covered by said source and drain electrodes by means of a mask, such that there remains a predetermined thickness of said n-type silicon layer; and doping said predetermined thickness of said n-type silicon layer with p-type impurities by means of a mask.
Claim 9
Dependent Claim
26 words
A method according to claim 6; wherein said step of removing includes the step of using said source electrode and said drain electrode as the mask.
Claim 10
Dependent Claim
30 words
A method according to claim 6; wherein said step of removing includes the step of using a resist layer formed on said source electrode and drain electrode as the mask.
Claim 11
Dependent Claim
25 words
A method according to claim 6; wherein said step of doping includes the step using said source electrode and said drain electrode as the mask.
Claim 12
Dependent Claim
25 words
A method according to claim 6; wherein said step of doping includes the step of forming said doped n-type silicon layer into an intrinsic layer.
Claim 13
Dependent Claim
25 words
A method according to claim 6; wherein said step of doping includes the step of forming said doped n-type silicon layer into a p-type layer.
Claim 14
Dependent Claim
30 words
A method according to claim 6; wherein said step of doping includes the step of using a resist layer formed on said source electrode and drain electrode as the mask.
Claim 15
Dependent Claim
31 words
A method according to claim 12; wherein said step of doping includes the step of forming said resist layer to have the shape of the source electrode and the drain electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |