US5111136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor circuit
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1991-08-14
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Granted: 1992-05-05
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Expires: 2011-08-14
Abstract
Abstract A test mode input detection circuit for a semiconductor device comprises a first circuit including a group of transistors and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a transistor whose gate receives an output from the output terminal of the first circuit, and a transistor whose gate receives a power source voltage, these transistors being connected in series between the power source and a ground, a node between the transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.
Inventors
- 👤 Hiromi Kawashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A semiconductor circuit comprising: a first circuit including a group of "n" transistors each having a threshold voltage of Vth to provide a collective threshold voltage of nVth, and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a first transistor whose gate receives an output from the output terminal of the first circuit, and a second transistor whose gate receives a power source voltage, the first and second transistors being connected in series between the power source and a ground, a node between the first and second transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.
Claim 2
Dependent Claim
149 words
A semiconductor circuit comprising: a first circuit including a group of "n" transistors each having a threshold voltage of Vth to provide a collective threshold voltage of nVth, and a load element, the transistors and load element being connected in series between a power source and an input terminal, a node between the transistor group and the load element forming an output terminal of the first circuit; a second circuit including a first transistor whose gate receives an output from the output terminal of the first circuit, and a second transistor whose gate receives a power source voltage, the first and second transistors being connected in series between the power source and a ground, a node between the first and second transistors forming an output terminal of the second circuit; and an inverter circuit for providing a test mode signal in response to an output of the second circuit.
Claim 3
Dependent Claim
33 words
A semiconductor circuit as set forth in claim 1, wherein the n transistors of the transistor group of the first circuit are n enhancement MOS transistors each having a short-circuited gate and drain.
Claim 4
Dependent Claim
28 words
A semiconductor circuit as set forth in claim 1, wherein the load element of the first circuit is a depletion MOS transistor having a short-circuited gate and source.
Claim 5
Dependent Claim
58 words
A semiconductor circuit as set forth in claim 1, wherein the size of each of the first and second transistors of the second circuit is determined such that, when a voltage higher than the power source voltage is applied to the input terminal, the second circuit provides an output voltage higher than a threshold voltage of the inverter.
Claim 6
Dependent Claim
20 words
A semiconductor circuit as set forth in claim 1, wherein the load element of the first circuit is a resistor.
Claim 7
Dependent Claim
52 words
A semiconductor circuit as set forth in claim 1, wherein said semiconductor circuit further includes an ordinary circuit which is connected to said input terminal, and said voltage detection circuit detecting an abnormal voltage outside a normal signal voltage range and applied to said input terminal and outputting a detection signal thereof.
Claim 8
Dependent Claim
27 words
A semiconductor circuit as set forth in claim 6, wherein said semiconductor circuit further includes a mode circuit which is activated in response to said detection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |