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US5017809A
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Method and apparatus for program verification of a field programmable logic device
Assignee: Lattice Semiconductor Corp
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Filing: 1989-10-23
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Granted: 1991-05-21
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Expires: 2009-10-23
Abstract
Abstract A program verification circuit and technique adapted for use with a programmable logic array having at least one logic gate and first and second inputs thereto. A unique and novel operation is afforded by the present invention in that a method is provided of verifying the program of a field programmable logic array having a logic gate and at least first and second inputs thereto. The method of the invention includes the steps of: a) shifting verification control data through a shift register; b) selecting the first input of the logic gate by applying a first control signal to the first input of the logic gate in response to the output of the shift register; and c) deselecting the second input of the logic gate in response to the output of the shift register. A particularly novel aspect of the invention is provided in that the step of shifting verification control data through the shift register includes the steps of providing a first control signal (e.g. a logical "0") for selecting an input (or column) of the logic gate and supplying a second control signal (e.g. a logical `1`) for deselecting all other inputs of the logic gate. The step of supplying a second control signal for deselecting all other inputs of the logic gate includes the step of supplying plural second control signals, one for n-1 deselected inputs of an n input logic gate.
Inventors
- 👤 John E. Turner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:22
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R31/318519; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
137 words
A program verification circuit for a programmable logic array having at least one logic gate and first and second inputs thereto, said program verification circuit comprising: shift register means for latching data, said shift register means including means for latching programming data in a first mode of operation and means for latching programming control data in a second mode of operation; and first multiplexer means for applying a first control signal to at least one of said inputs to said logic gate in response to the output of said shift register means, said first multiplexer means including verification control means for applying said first control signal to at least one of said inputs in response to the output of said shift register means in said second mode of operation in response to a first verification control signal.
Claim 2
Dependent Claim
137 words
A program verification circuit for a programmable logic array having at least one logic gate and first and second inputs thereto, said program verification circuit comprising: shift register means for latching data, said shift register means including means for latching programming data in a first mode of operation and means for latching programming control data in a second mode of operation; and first multiplexer means for applying a first control signal to at least one of said inputs to said logic gate in response to the output of said shift register means, said first multiplexer means including verification control means for applying said first control signal to at least one of said inputs in response to the output of said shift register means in said second mode of operation in response to a first verification control signal.
Claim 3
Dependent Claim
48 words
The invention of claim 1 wherein said first multiplexer means includes programming control means for applying the output of said shift register means to at least one of said inputs to said logic gate in said first mode of operation in response to a first programming control signal.
Claim 4
Dependent Claim
59 words
The invention of claim 2 wherein said programming control means includes a first transistor having a first terminal connected to the output of said shift register, a second terminal connected to a source of said first verification control signal, and a third terminal connected to said input of said logic gate, said second terminal being the control terminal thereof.
Claim 5
Dependent Claim
20 words
The invention of claim 3 wherein said first transistor of said first multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 6
Dependent Claim
21 words
The invention of claim 4 wherein said first transistor of said first multiplexer means is an n-channel complementary metal-oxide semiconductor transistor.
Claim 7
Dependent Claim
83 words
The invention of claim 3 wherein said verification control means includes second and third transistors, said third transistor having a first terminal connected to a first source of potential, a second terminal connected to the output of said shift register, and a third terminal connected to a first terminal of said second transistor, and said second transistor having a second terminal connected to a source of said first program control signal, and a third terminal connected to said input of said logic gate.
Claim 8
Dependent Claim
21 words
The invention of claim 6 wherein said second and third transistors of said first multiplexer means are complementary metal-oxide semiconductor transistors.
Claim 9
Dependent Claim
31 words
The invention of claim 7 wherein said second and third transistors of said first multiplexer means are n-channel complementary metal-oxide semiconductor transistors and said first source of potential is ground potential.
Claim 10
Dependent Claim
80 words
The invention of claim 1 wherein said means for latching programming data in a first mode of operation and said means for latching verification control data in a second mode of operation includes second multiplexer means connected to the input of said shift register means for gating said programming data in said first mode of operation and for providing at least some of said control signals in said second mode of operation in response to a second verification control signal.
Claim 11
Dependent Claim
59 words
The invention of claim 9 wherein said second multiplexer means includes a first transistor having a first terminal connected to a source of program data signals, a second terminal connected to the input of said shift register and a third terminal connected to a source of said second verification control signal, said second terminal being the control terminal thereof.
Claim 12
Dependent Claim
49 words
The invention of claim 10 wherein said second multiplexer means includes a second transistor having a first terminal connected to a source of potential, a second terminal connected to said source of said second verification control signal, and a third terminal connected to said input of said shift register.
Claim 13
Dependent Claim
20 words
The invention of claim 11 wherein said first transistor of said second multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 14
Dependent Claim
20 words
The invention of claim 12 wherein said second transistor of said second multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 15
Dependent Claim
21 words
The invention of claim 13 wherein said first transistor of said second multiplexer means is an n-channel complementary metal-oxide semiconductor transistor.
Claim 16
Dependent Claim
21 words
The invention of claim 14 wherein said second transistor of said second multiplexer means is a p-channel complementary metal-oxide semiconductor transistor.
Claim 17
Dependent Claim
14 words
The invention of claim 15 wherein said source of potential is not ground potential.
Claim 18
Dependent Claim
230 words
A program verification circuit for a programmable logic array having at least one logic gate and first and second inputs thereto, said program verification circuit comprising: shift register means including plural shift registers, one for each input to said logic gate, for latching programming data in a first mode of operation and for latching verification control data in a second mode of operation; first multiplexer means, including one multiplexer for each associated shift register, for applying a first control signal to one of said inputs to said logic gate in response to the output of an associated shift register, said first multiplexer means including: verification control means for applying said first control signal to at least one of said inputs in response to the output of said associated shift register in said second mode of operation in response to a first verification control signal and programming control means for applying the output of said associated shift register to at least one of said inputs to said logic gate in said first mode of operation in response to a first programming control signal; and second multiplexer means connected to the input of said shift register means for gating said programming data in said first mode of operation and for providing at least some of said control signals in said second mode of operation in response to a second verification control signal.
Claim 19
Dependent Claim
230 words
A program verification circuit for a programmable logic array having at least one logic gate and first and second inputs thereto, said program verification circuit comprising: shift register means including plural shift registers, one for each input to said logic gate, for latching programming data in a first mode of operation and for latching verification control data in a second mode of operation; first multiplexer means, including one multiplexer for each associated shift register, for applying a first control signal to one of said inputs to said logic gate in response to the output of an associated shift register, said first multiplexer means including: verification control means for applying said first control signal to at least one of said inputs in response to the output of said associated shift register in said second mode of operation in response to a first verification control signal and programming control means for applying the output of said associated shift register to at least one of said inputs to said logic gate in said first mode of operation in response to a first programming control signal; and second multiplexer means connected to the input of said shift register means for gating said programming data in said first mode of operation and for providing at least some of said control signals in said second mode of operation in response to a second verification control signal.
Claim 20
Dependent Claim
59 words
The invention of claim 17 wherein said verification control means includes a first transistor having a first terminal connected to the output of said shift register, a second terminal connected to a source of said first verification control signal, and a third terminal connected to said input of said logic gate, said second terminal being the control terminal thereof.
Claim 21
Dependent Claim
20 words
The invention of claim 18 wherein said first transistor of said first multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 22
Dependent Claim
21 words
The invention of claim 19 wherein said first transistor of said first multiplexer means is an n-channel complementary metal-oxide semiconductor transistor.
Claim 23
Dependent Claim
83 words
The invention of claim 18 wherein said programming control means includes second and third transistors, said third transistor having a first terminal connected to a first source of potential, a second terminal connected to the output of said shift register, and a third terminal connected to a first terminal of said second transistor, and said second transistor having a second terminal connected to a source of said first program control signal, and a third terminal connected to said input of said logic gate.
Claim 24
Dependent Claim
21 words
The invention of claim 21 wherein said second and third transistors of said first multiplexer means are complementary metal-oxide semiconductor transistors.
Claim 25
Dependent Claim
31 words
The invention of claim 22 wherein said second and third transistors of said first multiplexer means are n-channel complementary metal-oxide semiconductor transistors and said first source of potential is ground potential.
Claim 26
Dependent Claim
59 words
The invention of claim 17 wherein said second multiplexer means includes a first transistor having a first terminal connected to a source of program data signals, a second terminal connected to the input of said shift register and a third terminal connected to a source of said second verification control signal, said second terminal being the control terminal thereof.
Claim 27
Dependent Claim
49 words
The invention of claim 24 wherein said second multiplexer means includes a second transistor having a first terminal connected to a source of potential, a second terminal connected to said source of said second verification control signal, and a third terminal connected to said input of said shift register.
Claim 28
Dependent Claim
20 words
The invention of claim 25 wherein said first transistor of said second multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 29
Dependent Claim
20 words
The invention of claim 26 wherein said second transistor of said second multiplexer means is a complementary metal-oxide semiconductor transistor.
Claim 30
Dependent Claim
21 words
The invention of claim 27 wherein said first transistor of said second multiplexer means is an n-channel complementary metal-oxide semiconductor transistor.
Claim 31
Dependent Claim
21 words
The invention of claim 28 wherein said second transistor of said second multiplexer means is a p-channel complementary metal-oxide semiconductor transistor.
Claim 32
Dependent Claim
14 words
The invention of claim 29 wherein said source of potential is not ground potential.
Claim 33
Independent Claim
88 words
A method of verifying the program of a field programmable logic array having a logic gate and at least first and second inputs thereto, including the steps of: (a) shifting verification control data through a shift register; (b) selecting said first input of said logic gate by applying a first control signal to said first input of said logic gate in response to the output of said shift register; and (c) deselecting said second input of said logic gate in response to said output of said shift register.
Claim 34
Independent Claim
88 words
A method of verifying the program of a field programmable logic array having a logic gate and at least first and second inputs thereto, including the steps of: (a) shifting verification control data through a shift register; (b) selecting said first input of said logic gate by applying a first control signal to said first input of said logic gate in response to the output of said shift register; and (c) deselecting said second input of said logic gate in response to said output of said shift register.
Claim 35
Dependent Claim
49 words
The invention of claim 31 wherein said step of shifting verification control data through said shift register includes the steps of providing a first control signal for selecting an input of said logic gate and supplying a second control signal for deselecting all other inputs of said logic gate.
Claim 36
Dependent Claim
43 words
The invention of claim 32 wherein said step of supplying a second control signal for deselecting all other inputs of said logic gate includes the step of supplying plural second control signals, one for n-1 deselected inputs of an n input logic gate.
Claim 37
Independent Claim
197 words
A method of inputting and verifying a program in a field programmable logic array having a logic gate and at least first and second inputs thereto, said method including the steps of: (a) latching programming data into plural shift registers, in a first mode of operation, one for each input to said logic gate; (b) applying a control signal to each of said inputs to said logic gate in response to the output of an associated shift register by applying the output of said associated shift register to at least one of said inputs to said logic gate in response to a first programming control signal; (c) gating said programming data into said shift register in said first mode of operation; (d) latching verification control data into said shift registers, in a second mode of operation; (e) applying said first control signal to at least one of said inputs in response to the output of said associated shift register in said second mode of operation in response to a first verification control signal; and (f) gating at least some of said control signals in said second mode of operation in response to a second verification control signal.
Claim 38
Independent Claim
197 words
A method of inputting and verifying a program in a field programmable logic array having a logic gate and at least first and second inputs thereto, said method including the steps of: (a) latching programming data into plural shift registers, in a first mode of operation, one for each input to said logic gate; (b) applying a control signal to each of said inputs to said logic gate in response to the output of an associated shift register by applying the output of said associated shift register to at least one of said inputs to said logic gate in response to a first programming control signal; (c) gating said programming data into said shift register in said first mode of operation; (d) latching verification control data into said shift registers, in a second mode of operation; (e) applying said first control signal to at least one of said inputs in response to the output of said associated shift register in said second mode of operation in response to a first verification control signal; and (f) gating at least some of said control signals in said second mode of operation in response to a second verification control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |