Test interface for an MOS technology integrated circuit

Claim 1

A test interface for an MOS type integrated circuit including at least one function command input terminal, a test command input terminal and a test output terminal, characterized in that the interface comprises: a parallel circuit with head-to-tail connection of the source-drain paths of first and second MOS transistors of opposite types of conductivity, said parallel circuit being connected between a power supply voltage line of the integrated circuit and a potential point (V 2 ), the gate of said first transistor being connected to the test command input terminal and the gate of said second transistor being connected to said potential point; a third transistor (M5) having its drain-source path between said potential point and ground; a constant current source connected to the gate of said third transistor for supplying current to said second transistor when said first transistor is not conducting; detection means including a series cicruit between said power supply voltage and ground of the drain-source paths of a fourth transistor (M3) and a fifth transistor (M4) having opposite types of conductivity, whose common connection point is connected to the test output terminal, said fourth and fifth transistors forming a mirror-image current with said second (M2) and third (M5) transistors respectively, the gate of said fourth transistor being connected to said potential point for responding to the conduction of said parallel circuit, the gate of said fifth transistor being connected to the gate of said third transistor for receiving current from said constant current source; said series circuit responding to a voltage at the test input terminal higher than the power supply voltage, for providing a logic transition on the test output terminal when said first transistor is conducting.