Power up reset circuit

Claim 2

A reset circuit arrangement comprising: (a) reset circuitry having an input for connection with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output for connection with at least one circuit component to be reset, said circuitry providing a reset signal at said output upon initiation of said power supply voltage and until said power supply voltage reaches a predetermined level, at which time said reset signal is removed; (b) a latching circuit which forms part of said reset circuitry and which operates in a first unlatched state in response to and until said power supply voltage reaches said predetermined voltage level for maintaining said reset signal, at which time said latching circuit operates in a second latched state for removing said reset signal, said latching circuit operating in its second, latched state so long as said power supply voltage remains above said predetermined level; (c) means also forming part of said reset circuitry for grounding said latching circuit through a predetermined resistance; and (d) said latching circuit including a plurality of transistors having a common gate which is grounded through said predetermined resistance so as to rapidly direct voltage away from said common gate of said latching circuit for causing said latching circuit to switch to its first state in the event said power supply voltage is interrupted and for preventing any coupling or leakage of current to said gate from causing said latching circuit to latch prematurely when it is in its unlatched state.

Claim 3

A global reset circuit arrangement especially suitable for integration into a microprocessor, said circuit arrangement comprising: (a) means defining a circuit input to be connected with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time; (b) means defining a circuit output to be integrated into said microprocessor for connection with certain ones of its components to be reset to specific logic levels in response to the presence of a global reset signal at said output; (c) global reset circuitry electrically connected between said input and output and responsive to said power supply voltage as the latter, when activated, rises from its minimum level to its maximum level for providing said global reset signal at said output until said power supply voltage reaches a predetermined voltage level above its minimum level, at which time said reset signal is removed, said global reset circuitry including (i) a latching circuit which operates in a first state until said power supply voltage reaches said predetermined voltage level, at which time said latching circuit operates in a second state for removing said reset signal, (ii) means for latching said latching circuit into said second state at the time said power supply voltage reaches said predetermined voltage level and so long as said power supply voltage remains at or above said predetermined level, whereby to insure the continued absence of said reset signal, and (iii) means for grounding said latching circuit through a predetermined resistance so as to rapidly direct voltage away from said latching circuit sufficient to cause said latching circuit to switch to its first state in the event said power supply voltage falls below said predetermined level.

Claim 4

A global reset circuit arrangement especially suitable for integration into a microprocessor, said circuit arrangement comprising: (a) means defining a circuit input to be connected with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time; (b) means defining a circuit output to be integrated into said microprocessor for connection with certain ones of its components to be reset to specific logic levels in response to the presence of a global reset signal at said output; (c) global reset circuitry electrically connected between said input and output and responsive to said power supply voltage as the latter, when activated, rises from its minimum level to its maximum level for providing said global reset signal at said output until said power supply voltage reaches a predetermined voltage level above its minimum level, at which time said reset signal is removed, said global reset circuitry including (i) a latching circuit which operates in a first state until said power supply voltage reaches said predetermined voltage level, at which time said latching circuit operates in a second state for removing said reset signal, (ii) means for latching said latching circuit into said second state at the time said power supply voltage reaches said predetermined voltage level and so long as said power supply voltage remains at or above said predetermined level, whereby to insure the continued absence of said reset signal, and (iii) means for grounding said latching circuit through a predetermined resistance so as to rapidly direct voltage away from said latching circuit sufficient to cause said latching circuit to switch to its first state in the event said power supply voltage falls below said predetermined level.

Claim 5

A circuit arrangement according to claim 2 wherein said latching circuit includes three transistors.

Claim 6

A circuit arrangement according to claim 2 wherein said global reset circuitry is implemented in CMOS technology.

Claim 7

A circuit according to claim 2 wherein said predetermined resistance is 300K ohms.

Claim 8

A reset circuit arrangement comprising: (a) reset circuitry having an input connected with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output connected with at least one circuit component to be reset, said circuitry providing a reset signal at said ouput upon initiation of said power supply voltage and until said power supply voltage reaches a predetermined level, at which time said reset signal is removed; (b) a latching circuit which forms part of said reset circuitry and which operates in a first unlatched state in response to and until as said power supply voltage reaches said predetermined voltage level for maintaining said reset signal, at which time said latching circuit operates in a second latched state for removing said reset signal, said latching circuit operating in its second, latched state so long as said power supply voltage remains above said predetermined level; and (c) means also forming part of said reset circuitry for rapidly directing voltage away from said latched latching circuit sufficient to cause said latching circuit to switch to its first state in the event said power supply voltage is interrupted.

Claim 9

A reset circuit arrangement comprising: (a) reset circuitry having an input connected with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output connected with at least one circuit component to be reset, said circuitry providing a reset signal at said ouput upon initiation of said power supply voltage and until said power supply voltage reaches a predetermined level, at which time said reset signal is removed; (b) a latching circuit which forms part of said reset circuitry and which operates in a first unlatched state in response to and until as said power supply voltage reaches said predetermined voltage level for maintaining said reset signal, at which time said latching circuit operates in a second latched state for removing said reset signal, said latching circuit operating in its second, latched state so long as said power supply voltage remains above said predetermined level; and (c) means also forming part of said reset circuitry for rapidly directing voltage away from said latched latching circuit sufficient to cause said latching circuit to switch to its first state in the event said power supply voltage is interrupted.

Claim 10

A circuit arrangement according to claim 6 wherein said last-mentioned means includes means for grounding said latching circuit through a predetermined resistance.

Claim 11

A circuit arrangement according to claim 7 wherein said latching circuit includes three transistors, two of which have a common gate and wherein said common gate is grounded through said predetermined resistance.

Claim 12

A circuit arrangement according to claim 6 wherein said reset circuitry is implemented in CMOS technology.