US4045692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state binary logic signal source for electronic timepiece or the like
Assignee: Individual
•
Filing: 1975-09-23
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Granted: 1977-08-30
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Expires: 1995-09-23
Abstract
Abstract An inverting amplifier is provided with a high impedance input resistor connected at one end to an input terminal of the amplifier and connected at the other end to a first voltage source constituting a first binary logic level. The input terminal is also connected through a switch to a second voltage source constituting a second and opposite binary level. An MOS-FET has source and drain electrodes connected to the input terminal and the first voltage source respectively and a gate electrode connected to an output terminal of the amplifier. When the switch is closed, the second voltage is applied to the input terminal and the inverted output of the amplifier turns off the MOS-FET. When the switch is open, the first voltage is applied to the input terminal through the resistor and the inverted output of the amplifier turns on the MOS-FET. The low impedance of the MOS-FET in the turned on condition increases the stability of the amplifier under high humidity conditions.
Inventors
- 👤 Shigeru Morokawa
- 👤 Fukuo Sekiya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:37
CPC Classifications
G; G04; G04F; G04F5/00; G04G; G04G5/00; G04G5/02; H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
268 words
A solid state binary logic signal source for an electronic timepiece comprising: a first voltage source; a second voltage source; an input resistor connected to said first voltage source; a normally open switch connected to said second voltage source; a first inverting amplifier having an input terminal connected to said first and second voltage sources through said input resistor and said normally open switch, respectively, and an output terminal at which a first voltage equal to that of said second voltage source appears when said switch is open and a second voltage equal to that of said first voltage source appears when said switch is closed; a second inverting amplifier having an input terminal connected to the output terminal of said first inverting amplifier and an output terminal; and a field effect transistor connected between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier and having a gate electrode connected to the output terminal of said first inverting amplifier, said field effect transistor being normally turned on in response to said first voltage appearing at the output terminal of said first inverting amplifier to provide a low impedance path between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier, and said field effect transistor being turned off to provide a high impedance path between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier in response to said second voltage appearing at the output terminal of said first inverting amplifier when said switch is closed.
Claim 2
Dependent Claim
268 words
A solid state binary logic signal source for an electronic timepiece comprising: a first voltage source; a second voltage source; an input resistor connected to said first voltage source; a normally open switch connected to said second voltage source; a first inverting amplifier having an input terminal connected to said first and second voltage sources through said input resistor and said normally open switch, respectively, and an output terminal at which a first voltage equal to that of said second voltage source appears when said switch is open and a second voltage equal to that of said first voltage source appears when said switch is closed; a second inverting amplifier having an input terminal connected to the output terminal of said first inverting amplifier and an output terminal; and a field effect transistor connected between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier and having a gate electrode connected to the output terminal of said first inverting amplifier, said field effect transistor being normally turned on in response to said first voltage appearing at the output terminal of said first inverting amplifier to provide a low impedance path between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier, and said field effect transistor being turned off to provide a high impedance path between the input terminal of said first inverting amplifier and the output terminal of said second inverting amplifier in response to said second voltage appearing at the output terminal of said first inverting amplifier when said switch is closed.
Claim 3
Dependent Claim
27 words
A solid state binary logic signal source according to claim 1, in which said field effect transistor comprises an n-channel type metal oxide semiconductor field effect transistor.
Claim 4
Dependent Claim
27 words
A solid state binary logic signal source according to claim 1, in which said field effect transistor comprises a p-channel type metal oxide semiconductor field effect transistor.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |