Patent US5093713A successfully refreshed from Google Patents.
US5093713A
Expired / Lapsed
US
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Semiconductor device package
Assignee: Toshiba Corp
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Filing: 1991-05-08
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Granted: 1992-03-03
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Expires: 2011-05-08
Abstract
Abstract A semiconductor device package includes a first semiconductor chip. The first semiconductor chip is mounted on a substrate island region. A lead frame is arranged to serve as an external terminal of the first semiconductor chip, and includes an island region for mounting at least one second semiconductor chip.
Inventors
- 👤 Hiromichi Sawaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:08
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W90/00; H10W90/811; H10W40/00; H10W40/10; H10W40/70; H10W40/77; H10W40/778; H10W74/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
67 words
A resin-sealed semiconductor device package, comprising: a first semiconductor chip; a substrate island region for mounting said first semiconductor chip; lead frame means, arranged to serve as an external terminal of said first semiconductor chip, and including an island region for mounting at least one second semiconductor chip; and a resin layer for thermally and electrically insulating said second semiconductor chip from said a first semiconductor chip.
Claim 2
Dependent Claim
67 words
A resin-sealed semiconductor device package, comprising: a first semiconductor chip; a substrate island region for mounting said first semiconductor chip; lead frame means, arranged to serve as an external terminal of said first semiconductor chip, and including an island region for mounting at least one second semiconductor chip; and a resin layer for thermally and electrically insulating said second semiconductor chip from said a first semiconductor chip.
Claim 3
Dependent Claim
15 words
A package according to claim 1, wherein said substrate island region constitutes a heat-radiation fin.
Claim 4
Dependent Claim
23 words
A package according to claim 1, which further comprises a solder layer for fixing said first semiconductor chip to said substrate island region.
Claim 5
Dependent Claim
21 words
A package according to claim 1, which further comprises a bonding wire for electrically connecting said first and second semiconductor chips.
Claim 6
Dependent Claim
51 words
A package according to claim 1, wherein an upper limit of a distance along a surface of said substrate island region between an end of said first semiconductor chip and a distal end of said lead frame means is 2.5 to 3 mm, and a lower limit thereof is 0.5 mm.
Claim 7
Dependent Claim
38 words
A package according to claim 1, wherein a distance along a surface of said substrate island region between an end of said first semiconductor chip and a distal end of said lead frame means is about 1 mm.
Claim 8
Dependent Claim
27 words
A package according to claim 1, wherein a distance from a distal end of said lead frame means to said second semiconductor chip is about 1.4 mm.
Claim 9
Dependent Claim
26 words
A package according to claim 1, wherein a height of said lead frame means from a surface of said substrate island region is about 0.5 mm.
Claim 10
Dependent Claim
18 words
A package according to claim 1, wherein said first and second semiconductor chips are bonded by different methods.
Claim 11
Dependent Claim
29 words
A package according to claim 11, wherein said first semiconductor chip is fixed by a solder bonding method, and said second semiconductor chip is fixed by a conductive adhesive.
Claim 12
Dependent Claim
25 words
A package according to claim 11, wherein said first semiconductor chip is bonded by an AuSi eutectic alloy method, and said second semiconductor chip is
Claim 13
Dependent Claim
15 words
A package according to claim 1, wherein said second semiconductor chip is fixed by calking.
Claim 14
Dependent Claim
31 words
A package according to claim 1, wherein said first semiconductor chip has a first substrate potential, and secured semiconductor chip has a second substrate potential different from the first substrate potential.
References Cited (Backward Citations)
US3639770A
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US3715633A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-03 | 1995-09-02 | 1996-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-03 | 1999-09-02 | 2000-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-03 | 2003-09-02 | 2004-03-03 | $7700.00 | Window Closed / Lapsed |