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US5086005A Expired / Lapsed US ⏱️ 0.0 years remaining

Bipolar transistor and method for manufacturing the same

Assignee: Toshiba Corp
•
Filing: 1990-06-05
•
Granted: 1992-02-04
•
Expires: 2010-06-05
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Abstract

Abstract In a self-alignment type-lateral bipolar transistor and a manufacturing method thereof, the base width is determined not by the image resolution limit of the lithography technique, as in the prior art, but by the impurity diffusion from the polysilicon layer 118. Therefore, the self-alignment type lateral-structure pnp bipolar transistor and the manufacturing method permit the base width to be as small as possible, resulting in improvement of frequency characteristics, and reducing the size of the transistor element.

Inventors

  • 👤 Kenji Hirakawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 00:03
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/184; H10D10/00; H10D10/01; H10D10/051; H10D10/60; Y; Y10; Y10S; Y10S148/00; Y10S148/01

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 483 words
A method for manufacturing a bipolar transistor, comprising the steps of: forming a first insulation film on a semiconductor substrate; exposing a predetermined surface portion of the semiconductor substrate by selectively removing the first insulation film; forming a first polycrystalline semiconductor layer on the resultant semiconductor structure; forming a first photoresist film having a predetermined pattern on the first polycrystalline semiconductor layer; ion-implanting first impurities, which are of a first conductivity type, into the first polycrystalline semiconductor layer, using the first photoresist film as a mask; removing the first photoresist film; ion-implanting second impurities, which are of a second conductivity type and have a larger diffusion coefficient than that of the first impurities, into the first polycrystalline semiconductor layer through the entire surface thereof; forming a second insulation film on the first polycrystalline semiconductor layer; forming a second photoresist film having a predetermined pattern on the second insulation film; forming an opening to expose a predetermined surface portion of the semiconductor substrate by selectively removing the second insulation film and the first polycrystalline semiconductor layer, using the second photoresist film as a mask, such that the first polycrystalline semiconductor layer is divided into: a second polycrystalline semiconductor layer containing both impurities of the first conductivity type and impurities of the second conductivity type; and a third polycrystalline semiconductor layer containing only impurities of the second conductivity type; removing the second photoresist films; forming a third insulation film on the resultant semiconductor structure; exposing the predetermined surface portion of the semiconductor substrate once again, by selectively removing the third insulation film such that the third insulation film remains on side walls of the opening; heat-treating the resultant semiconductor structure, so as both to form a fourth insulation film on the exposed surface portion of the semiconductor substrate and to activate the first and second impurities such that the semiconductor substrate contains: a first impurity-diffusion layer which is of the second conductivity type; a second impurity-diffusion layer which is of the first conductivity and is in contact with the first impurity-diffusion layer; and a third impurity-diffusion layer of the second conductivity; ion-implanting third impurities of the first conductivity type into the fourth insulation film; forming a fourth impurity-diffusion layer, which is of the first conductivity type and is in contact with both the second and third impurity-diffusion layers, by activating the third impurities implanted into the fourth insulation film; exposing the predetermined surface portion of the semiconductor substrate once again, by removing the fourth insulation film; forming a fourth polycrystalline semiconductor layer, which contains fourth impurities of the second conductivity, on the entire surface of the resultant semiconductor structure; and forming a fifth impurity-diffusion layer, which is of the first conductivity type, is located inside the fourth impurity-diffusion layer, and is contact with the second impurity-diffusion layer, by activating the fourth impurities to diffuse from the fourth polycrystalline semiconductor layer into the fourth impurity-diffusion layer.
Claim 2
Independent Claim 483 words
A method for manufacturing a bipolar transistor, comprising the steps of: forming a first insulation film on a semiconductor substrate; exposing a predetermined surface portion of the semiconductor substrate by selectively removing the first insulation film; forming a first polycrystalline semiconductor layer on the resultant semiconductor structure; forming a first photoresist film having a predetermined pattern on the first polycrystalline semiconductor layer; ion-implanting first impurities, which are of a first conductivity type, into the first polycrystalline semiconductor layer, using the first photoresist film as a mask; removing the first photoresist film; ion-implanting second impurities, which are of a second conductivity type and have a larger diffusion coefficient than that of the first impurities, into the first polycrystalline semiconductor layer through the entire surface thereof; forming a second insulation film on the first polycrystalline semiconductor layer; forming a second photoresist film having a predetermined pattern on the second insulation film; forming an opening to expose a predetermined surface portion of the semiconductor substrate by selectively removing the second insulation film and the first polycrystalline semiconductor layer, using the second photoresist film as a mask, such that the first polycrystalline semiconductor layer is divided into: a second polycrystalline semiconductor layer containing both impurities of the first conductivity type and impurities of the second conductivity type; and a third polycrystalline semiconductor layer containing only impurities of the second conductivity type; removing the second photoresist films; forming a third insulation film on the resultant semiconductor structure; exposing the predetermined surface portion of the semiconductor substrate once again, by selectively removing the third insulation film such that the third insulation film remains on side walls of the opening; heat-treating the resultant semiconductor structure, so as both to form a fourth insulation film on the exposed surface portion of the semiconductor substrate and to activate the first and second impurities such that the semiconductor substrate contains: a first impurity-diffusion layer which is of the second conductivity type; a second impurity-diffusion layer which is of the first conductivity and is in contact with the first impurity-diffusion layer; and a third impurity-diffusion layer of the second conductivity; ion-implanting third impurities of the first conductivity type into the fourth insulation film; forming a fourth impurity-diffusion layer, which is of the first conductivity type and is in contact with both the second and third impurity-diffusion layers, by activating the third impurities implanted into the fourth insulation film; exposing the predetermined surface portion of the semiconductor substrate once again, by removing the fourth insulation film; forming a fourth polycrystalline semiconductor layer, which contains fourth impurities of the second conductivity, on the entire surface of the resultant semiconductor structure; and forming a fifth impurity-diffusion layer, which is of the first conductivity type, is located inside the fourth impurity-diffusion layer, and is contact with the second impurity-diffusion layer, by activating the fourth impurities to diffuse from the fourth polycrystalline semiconductor layer into the fourth impurity-diffusion layer.

References Cited (Backward Citations)

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US3919005A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-02-03 1995-08-05 1996-02-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-02-03 1999-08-05 2000-02-04 $3760.00 Window Closed / Lapsed
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