Packaging for multiple chips on a single leadframe

Claim 2

A lead frame assembly for receiving multiple integrated circuit chips on one side thereof, the integrated circuit chips each having active circuitry on one side and having a substrate contact on an opposite side, the lead frame assembly comprising: (a) at least one side rail; (b) a plurality of leads depending from at least one rail; (c) a first die attach paddle, connected to a first rail by a first lead, for receiving a first substrate bias voltage for application to the substrate contact of a first one of the chips; (d) a second die attach paddle connected to a rail by a second lead, for receiving a second substrate bias voltage for application to the substrate contact of a second one of the chips, such that the second die attach paddle and second chip substrate will be electrically isolated from the first die attach paddle and first chip substrate after the rails are cut away from the leads; and (e) a dielectric tape adhered to one side of the first and second die attach paddles to support the die attach paddles and limit relative motion therebetween, to permit direct chip-to-chip wiring connections, said side being the side of the paddles opposite the side which will receive the integrated circuit chips.

Claim 3

A leadframe assembly according to claim 1, said leadframe assembly further including a first side rail and a second side rail, the first die paddle being suspended from the second side rail, and wherein the dielectric tape is attached to one surface of the die attach paddles, whereby motion of the die attach paddles relative to each other is substantially prevented.

Claim 4

An integrated circuit package comprising: (a) first and second integrated circuit chips, each including active circuitry on one side and including a substrate contact on an opposite side; (b) a lead frame assembly including at least one side rail, a plurality of leads, a first die attach paddle connected to a first rail by a first lead, for receiving a first substrate bias voltage, and a second die attach paddle connected to a rail by a second lead, for a receiving a second substrate bias voltage, such that the second die attach paddle will be electrically isolated from the first die attach paddle, after the rails are cut away from the leads; (c) the first and second integrated circuit chips being secured, respectively, to the first and second die attach paddles, such that the substrate contact of each makes electrical contact, respectively, with the first and second die attach paddles; (d) a dielectric tape adhered to one side of the first and second die attach paddles to support the die attach paddles and limit relative motion therebetween, to permit direct electrical interconnections between circuitry of the first and second integrated circuits within the package, said side being the side of the paddles opposite the side which will receive the integrated circuit chips; and (e) electrical interconnections between circuitry of the first and second integrated circuits within the package.

Claim 5

An integrated circuit package comprising: (a) first and second integrated circuit chips, each including active circuitry on one side and including a substrate contact on an opposite side; (b) a lead frame assembly including at least one side rail, a plurality of leads, a first die attach paddle connected to a first rail by a first lead, for receiving a first substrate bias voltage, and a second die attach paddle connected to a rail by a second lead, for a receiving a second substrate bias voltage, such that the second die attach paddle will be electrically isolated from the first die attach paddle, after the rails are cut away from the leads; (c) the first and second integrated circuit chips being secured, respectively, to the first and second die attach paddles, such that the substrate contact of each makes electrical contact, respectively, with the first and second die attach paddles; (d) a dielectric tape adhered to one side of the first and second die attach paddles to support the die attach paddles and limit relative motion therebetween, to permit direct electrical interconnections between circuitry of the first and second integrated circuits within the package, said side being the side of the paddles opposite the side which will receive the integrated circuit chips; and (e) electrical interconnections between circuitry of the first and second integrated circuits within the package.

Claim 6

An integrated circuit assembly comprising: (a) first and second integrated circuit chips, each including active circuitry on one side and including a substrate contact on an opposite side; (b) a leadframe assembly including a plurality of leads, a first die attach paddle connected to a first lead, for receiving a first substrate bias voltage, and a second die attach paddle connected to a second lead, for receiving a second substrate bias voltage, such that the second die attach paddle is electrically isolated from the first die attach paddle; (c) the first and second integrated circuit chips being secured, respectively, to one side of the first and second die attach paddles, such that the substrate contact of each makes electrical contact, respectively, with the first and second die attach paddles; (d) a dielectric tape adhered to a second side of the first and second die attach paddles to support the die attach paddles and limit relative motion therebetween, to permit direct electrical interconnections between circuitry of the first and second integrated circuits within the package.

Claim 7

An integrated circuit assembly comprising: (a) first and second integrated circuit chips, each including active circuitry on one side and including a substrate contact on an opposite side; (b) a leadframe assembly including a plurality of leads, a first die attach paddle connected to a first lead, for receiving a first substrate bias voltage, and a second die attach paddle connected to a second lead, for receiving a second substrate bias voltage, such that the second die attach paddle is electrically isolated from the first die attach paddle; (c) the first and second integrated circuit chips being secured, respectively, to one side of the first and second die attach paddles, such that the substrate contact of each makes electrical contact, respectively, with the first and second die attach paddles; (d) a dielectric tape adhered to a second side of the first and second die attach paddles to support the die attach paddles and limit relative motion therebetween, to permit direct electrical interconnections between circuitry of the first and second integrated circuits within the package.

Claim 8

An integrated circuit assembly as in claim 4, further comprising: a bond wire connected directly between said first and second integrated circuit chips to effect an electrical connection between circuitry therein.