Semiconductor integrated circuit device and wiring method thereof

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a plurality of basic cell lines each of which arranges basic cells having a plurality of transistors, said basic cell lines being positioned at an internal circuit area on said main surface of the semiconductor substrate; output buffer circuits being formed in input/output (I/O) areas on said main surface of the semiconductor substrate and being positioned around said internal circuit area, said output buffer circuits including first output buffer circuits which are characterized as providing output levels, at respective outputs thereof, which switch substantially simultaneously from one level to another level thereof and second output buffer circuits which are characterized as providing output levels, at respective outputs thereof, associated with switching times that are not simultaneous with that of a said first output buffer circuits; a first wiring, extending on said I/O areas, for supplying a first fixed potential to said first output buffer circuits; and a second wiring, extending on said I/O areas, for supplying the first fixed potential to said second output buffer circuits, said second wiring being separated from said first wiring.

Claim 3

A semiconductor integrated device according to claim 1, wherein said semiconductor integrated circuit device is a gate array type semiconductor integrated circuit device.

Claim 4

A semiconductor integrated circuit device according to claim 1, wherein each one of said basic cells comprises p-channel MISFETs and N-channel MISFETs.

Claim 5

A semiconductor integrated circuit device according to claim 1, wherein said first wiring corresponds to a same level metal wiring which is formed on said semiconductor substrate as said second wiring.

Claim 6

A semiconductor integrated circuit device according to claim 1, wherein said first wiring is a reference voltage wiring.

Claim 7

A semiconductor integrated circuit device according to claim 1, which further includes: a third wiring for supplying a second fixed potential to said first and second output buffer circuits, said third wiring extending on said I/O areas; a fourth wiring, extending on said I/O areas, for supplying said first fixed potential to said internal circuit area and to input buffer circuits formed in said I/O areas; and a fifth wiring, extending on said I/O areas, for supplying said second fixed potential to said internal circuit area and to said input buffer circuits.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said first fixed potential is a reference potential and said second fixed potential is a power source potential.

Claim 9

A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; internal circuits being disposed at an internal circuit area on said main surface of the semiconductor substrate; output buffer circuits being formed input/output (I/O) areas on said main surface of the semiconductor substrate and being disposed around said internal circuit area, said output buffer circuits including first output buffer circuits which are characterized as providing output levels, at respective outputs thereof, which switch substantially simultaneously from one to another level thereof and second output buffer circuits which are characterized as providing output levels, at respective outputs thereof, associated with switching times that are not simultaneous with that of said first output buffer circuits; a first wiring, extending on said I/O areas, for supplying a first fixed potential to said first output buffer circuits; and a second wiring, extending on said I/O areas, for supplying said first fixed potential to said second output buffer circuits, said second wiring being separated from said first wiring.

Claim 10

A semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; internal circuits being disposed at an internal circuit area on said main surface of the semiconductor substrate; output buffer circuits being formed input/output (I/O) areas on said main surface of the semiconductor substrate and being disposed around said internal circuit area, said output buffer circuits including first output buffer circuits which are characterized as providing output levels, at respective outputs thereof, which switch substantially simultaneously from one to another level thereof and second output buffer circuits which are characterized as providing output levels, at respective outputs thereof, associated with switching times that are not simultaneous with that of said first output buffer circuits; a first wiring, extending on said I/O areas, for supplying a first fixed potential to said first output buffer circuits; and a second wiring, extending on said I/O areas, for supplying said first fixed potential to said second output buffer circuits, said second wiring being separated from said first wiring.

Claim 11

A semiconductor integrated circuit device according to claim 8, further including: a third wiring, extending on said I/O areas, for supplying a second fixed potential to said first and second output buffer circuits.

Claim 12

A semiconductor integrated circuit device according to claim 9, further including: a first bonding pad for said first fixed potential electrically connected to said first wiring, and a second bonding pad for said first fixed potential electrically connected to said second wiring.

Claim 13

A semiconductor integrated circuit device according to claim 10, wherein said first fixed potential is a reference potential, and said second fixed potential is a power source potential.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said I/O areas are disposed so as to surround said internal circuit area.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein the first and second bonding pads are disposed on said semiconductor substrate further away from said internal circuit area than are said I/O areas.

Claim 16

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area and input/output (I/O) areas which are disposed around said internal circuit area, said I/O areas corresponding to areas where input buffer circuits and output buffer circuits are to be formed, and said internal circuit area corresponding to an area where internal circuits are to be formed, a method of designing wirings for supplying a fixed potential to said I/O areas, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are separated with a predetermined distance mutually; and disposing a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where said connection patterns are disposed and those portions where they are not disposed.

Claim 17

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area and input/output (I/O) areas which are disposed around said internal circuit area, said I/O areas corresponding to areas where input buffer circuits and output buffer circuits are to be formed, and said internal circuit area corresponding to an area where internal circuits are to be formed, a method of designing wirings for supplying a fixed potential to said I/O areas, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are separated with a predetermined distance mutually; and disposing a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where said connection patterns are disposed and those portions where they are not disposed.

Claim 18

A semiconductor integrated circuit device according to claim 14, wherein said first fixed potential is a reference potential.

Claim 19

A semiconductor integrated circuit device according to claim 15, wherein said I/O areas are disposed so as to surround said internal circuit area, and said wirings are formed to extend on said I/O areas.

Claim 20

A designing method of wirings according to claim 15, wherein said connection patterns are disposed between fixed patterns on said adjacent I/O areas such that a wiring which is effected for supplying said fixed potential to a group from said output buffer circuits whose outputs switch simultaneously is laid out separately from other ones of said wirings for supplying said fixed potential to other ones of said output buffer circuits.

Claim 21

A designing method of wirings according to claim 17, wherein said fixed pattern and said connection pattern are formed by an electrically conductive layer corresponding to a same level layer as that of said wirings.

Claim 22

A designing method of wirings according to claim 18, wherein said designing method is employed by Design Automation.

Claim 23

A designing method of wirings according to claim 17, wherein said connection pattern is formed by an electrically conductive layer corresponding to a higher level layer than that of said fixed pattern.

Claim 24

A designing method of wirings according to claim 20, wherein said designing method is employed by Design Automation.

Claim 25

A designing method of wirings according to claim 15, wherein said fixed pattern and said connection pattern are formed by an electrically conductive layer corresponding to a same level layer as that of said wirings.

Claim 26

A designing method of wirings according to claim 15, wherein said designing method is employed by Design Automation.

Claim 27

A designing method of wirings according to claim 15, wherein said connectioin pattern is formed by an electrically conductive layer corresponding to a higher level layer than that of said fixed pattern.

Claim 28

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area and input/output (I/O) areas which are disposed so as to surround said internal circuit area, said I/O areas corresponding to areas where input buffer circuits and output buffer circuits are to be formed, and said internal circuit area corresponding to an area where internal circuits are to be formed, a method of designing wirings, which extend on said I/O areas, for supplying a reference potential to said I/O areas, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are separated with a predetermined distance mutually; and arranging a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where connection portions for electrically connecting between said connection pattern and said fixed patterns on said adjacent I/O areas are disposed and those portions were they are not disposed.

Claim 29

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area and input/output (I/O) areas which are disposed so as to surround said internal circuit area, said I/O areas corresponding to areas where input buffer circuits and output buffer circuits are to be formed, and said internal circuit area corresponding to an area where internal circuits are to be formed, a method of designing wirings, which extend on said I/O areas, for supplying a reference potential to said I/O areas, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are separated with a predetermined distance mutually; and arranging a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where connection portions for electrically connecting between said connection pattern and said fixed patterns on said adjacent I/O areas are disposed and those portions were they are not disposed.

Claim 30

A designing method of wirings according to claim 25, wherein said connection pattern is formed by an electrically conductive layer corresponding to a higher level layer than that of said fixed pattern.

Claim 31

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area including a plurality of basic cell lines each formed by arranging repeatedly basic cells each having a plurality of transistors formed on a semiconductor substrate; and input/output (I/O) areas disposed at peripheral portions of said internal circuit area and having formed therein input buffer circuits and output buffer circuits, wherein a a plurality of said output buffer circuits have outputs providing output levels which switch substantially simultaneously from one level to another level thereof, a method of designing wirings which extend on said I/O areas and supply a fixed potential to said output buffer circuits, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are not connected mutually; and disposing a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where said connection patterns are disposed and those portions where they are not disposed.

Claim 32

In a semiconductor integrated circuit device including a semiconductor substrate having a main surface which has an internal circuit area including a plurality of basic cell lines each formed by arranging repeatedly basic cells each having a plurality of transistors formed on a semiconductor substrate; and input/output (I/O) areas disposed at peripheral portions of said internal circuit area and having formed therein input buffer circuits and output buffer circuits, wherein a a plurality of said output buffer circuits have outputs providing output levels which switch substantially simultaneously from one level to another level thereof, a method of designing wirings which extend on said I/O areas and supply a fixed potential to said output buffer circuits, said method comprising the steps of: arranging a fixed pattern of said wirings for each of said I/O areas such that said fixed patterns of said I/O areas adjacent to one another are not connected mutually; and disposing a connection pattern for connecting mutually said fixed patterns located on said adjacent I/O areas, thereby effecting a connection of the fixed patterns between adjacent I/O areas in the arrangement such that there exist between said fixed patterns on said adjacent I/O areas those portions where said connection patterns are disposed and those portions where they are not disposed.

Claim 33

A designing method of wirings according to claim 27, wherein said connection patterns are disposed between fixed patterns on said adjacent I/O areas such that a wiring which is effected for supplying said fixed potential to said plurality of output buffer circuits whose outputs switch simultaneously is laid out separately from other ones of said wirings for supplying said fixed potential to other ones of said output buffer circuits.

Claim 34

A designing method of wirings according to claim 28, wherein said fixed pattern and said connection pattern are formed by an electrically conductive layer corresponding to a same level layer as that of said wiring.

Claim 35

A designing method of wirings according to claim 28, wherein said connection pattern is formed by an electrically conductive layer corresponding to a higher level layer than that of said fixed pattern.

Claim 36

A designing method of wirings according to claim 28, wherein said designing method is employed by Design Automation.

Claim 37

A designing method of wirings according to claim 27, wherein said fixed pattern and said connection pattern are formed by an electrically conductive layer corresponding to a same level layer as that of said wirings.

Claim 38

A designing method of wirings according to claim 27, wherein said connection pattern is formed by an electrically conductive layer corresponding to a higher level layer than that of said fixed pattern.

Claim 39

A designing method of wirings according to claim 27, wherein said designing method is employed by Design Automation.