EP0278857A2
Expired / Lapsed
EP
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Master slice type integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1988-02-02
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Granted: —
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Expires: 2008-02-02
Abstract
Abstract A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells (21a - 21d) arranged in a peripheral region on a semiconductor chip (60), the input/output cells each comprising pads (22a - 22d) for connection with an external circuit, input wiring regions (25a - 25d) each for accommodating input interconnecting lines (41, 46, 47) carrying input signals, and output circuit regions (24a - 24d) each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surounded by the arrangement of the input/output cells. Two adjacent input/output cells (21a, 21b; 21c, 21d) are paired with each other. The output circuit regions (24a, 24b; 24c, 24d) of the pair of the input/output cells are arranged in the vicinity of a boundary (L₁; L₂) of the pair. The input wiring regions (25a, 25b; 25c, 25d) of the pair are arranged in the vicinity of boundaries with respect to other pairs.
Inventors
- 👤 Masayuki Naganuma
- 👤 Yoshiyuki Suehiro
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 18:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W20/00; H10W20/40; H10W20/49
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
172 words
A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprising a plurality of input/output cells (21a - 21d) arranged in a peripheral region on a semiconductor chip (60), the input/output cells each comprising pads (22a - 22d) for connection with an external circuit, input wiring regions (25a - 25d) each for accommodating input interconnecting lines (41, 46, 47) carrying input signals, and output circuit regions (24a - 24d) each for forming output buffers; and a plurality of basic cells (65) being arranged in a region on the chip surrounded by the arrangement of the input/output cells, characterized in that two adjacent input/output cells (21a, 21b; 21c, 21d) are paired with each other, and the output circuit regions (24a, 24b; 24c, 24d) of the pair of the input/output cells are arranged in the vicinity of a boundary (L₁; L₂) of the pair, and the input wiring regions (25a, 25b; 25c, 25d) of the pair are arranged in the vicinity of boundaries with respect to other pairs.
Claim 2
Dependent Claim
172 words
A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprising a plurality of input/output cells (21a - 21d) arranged in a peripheral region on a semiconductor chip (60), the input/output cells each comprising pads (22a - 22d) for connection with an external circuit, input wiring regions (25a - 25d) each for accommodating input interconnecting lines (41, 46, 47) carrying input signals, and output circuit regions (24a - 24d) each for forming output buffers; and a plurality of basic cells (65) being arranged in a region on the chip surrounded by the arrangement of the input/output cells, characterized in that two adjacent input/output cells (21a, 21b; 21c, 21d) are paired with each other, and the output circuit regions (24a, 24b; 24c, 24d) of the pair of the input/output cells are arranged in the vicinity of a boundary (L₁; L₂) of the pair, and the input wiring regions (25a, 25b; 25c, 25d) of the pair are arranged in the vicinity of boundaries with respect to other pairs.
Claim 3
Dependent Claim
63 words
A master slice type integrated circuit as claimed in claim 1, characterized in that the pair of the input/out cells (21a, 21b; 21c, 21d) has a reflection relationship in which the output circuit regions (24a, 24b; 24c, 24d) and the input wiring regions (25a, 25b; 25c, 25d) of the pair are symmetrically located opposite each other with respect to the boundary (L₁; L₂).
Claim 4
Dependent Claim
52 words
A master slice type integrated circuit as claimed in any of claims 1 and 2, characterized in that each of the output circuit regions includes a region (34a - 34d) for forming an n-channel metal oxide semiconductor transistor and a region (35a - 35d) for forming a p-channel metal oxide semiconductor region.
Claim 5
Dependent Claim
38 words
A master slice type integrated circuit as claimed in claim 3, characterized in that the n-channel and p-channel metal oxide semiconductor regions of the pair of input/output cells are close to each other through respective source regions (d).
Claim 6
Dependent Claim
57 words
A master slice type integrated circuit as claimed in any of claims 1 to 4, characterized in that an interconnecting line (40 - 50) for transmitting a signal is formed by a first metallization layer and a power supply line for supplying a power to circuits constituted in the chip is formed by a second metallization layer.
Claim 7
Dependent Claim
30 words
A master slice type integrated circuit as claimed in any of claims 1 to 5, characterized in that adjacent pairs (62, 63) of input/output cells are close to each other.
Claim 8
Dependent Claim
30 words
A master slice type integrated circuit as claimed in any of claims 1 to 5, characterized in that adjacent pairs (62, 63) of input/output cells are spaced a predetermined distance.
Claim 9
Dependent Claim
66 words
A master slice type integrated circuit as claimed in any of claims 1 to 7, characterized in that each of the input/output cells (21a - 21d) of the master slice type integrated circuit further comprises an input protecting circuit region (23a - 23d) for forming a protection circuit which has a function of protecting an input buffer composed of the basic cells against an electrostatic discharge.
Claim 10
Dependent Claim
95 words
A master slice type integrated circuit as claimed in claim 8, characterized in that the pair of input/output cells (21a, 21b) comprises a first interconnection line (41, 42) extending from the pad (22a) of one input/output cell (21a) of the pair to the input buffer through the input protecting circuit region (23a) and the input circuit region (25a), and a second interconnection line (42) which connects the pad (22b) of the other input/output cell of the pair to the n- and p-channel MOS transistor regions (34a, 34b, 35a, 35b) of the pair of input/output cells.
Claim 11
Dependent Claim
91 words
A master slice type integrated circuit as claimed in claim 8, characterized in that the pair of input/output cells (21c, 21d) comprises a first interconnecting line (45, 46) which connects the pad (22c) of one input/output cell of the pair to the input buffer through the input protecting region (23c) and the input wiring region (25c), and a second interconnecting line (45) which couples the pad (22c) of said one input/output cell (21c) of the pair to the n- and p-channel MOS transistor regions (34c, 34d, 35c, 35d) of the pair.
Claim 12
Dependent Claim
33 words
A master slice type integrated circuit as claimed in claim 3, characterized in that the output buffer is an inverter (34) composed of the pair of n- and p-channel metal oxide semiconductor transistors.
Claim 13
Dependent Claim
41 words
A master slice type integrated circuit as claimed in claim 3, characterized in that the output buffer is made up of inverters connected in parallel, each of which is composed of the pair of n- and p-channel metal oxide semiconductor transistors.
Claim 14
Dependent Claim
102 words
A master slice type integrated circuit as claimed in any of claims 1 to 12, characterized in that the input protecting circuit region (23a, 23b, 23c, 23d) comprises an input terminal (30), a first diode (D₁) having a cathode connected to a positive power supply terminal (32) and an anode connected to the input terminal, a second diode (D₂) having a cathode connected to the input terminal and an anode connected to a negative power supply terminal (33), a resistor (R₁) having an end connected to the input terminal, and an output terminal (31) connected to the other end of the resistor.
References Cited (Backward Citations)
No citation records indexed.
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