Monolithic integration of silicon on insulator and gallium arsenide semiconductor technologies

Claim 2

A process for preparing a semiconductor heterostructure, comprising the steps of: furnishing a silicon-on-insulator substrate having a device quality silicon layer on an insulator substrate; forming a transition layer of gallium arsenide directly on the silicon layer, the transition layer being deposited at a temperature of about 40° C. to about 100° C. and then regrown by solid phase epitaxy on the silicon layer; and forming a primary epitaxial layer of a material selected from the group consisting of gallium arsenide and alloys thereof directly on the transition layer.

Claim 3

The process of claim 1, wherein the insulator substrate is a material selected from the group consisting of Al 2 O 3 and SiO 2 .

Claim 4

The process of claim 1, wherein the transition layer is about 200 Angstroms thick.

Claim 5

The process of claim 1, wherein the primary layer is formed by deposition using molecular beam epitaxy.

Claim 6

The process of claim 1, wherein the primary layer is from about 100 Angstroms to about 50 micrometers thick.

Claim 7

The process of claim 1, including the further step of forming a microelectronic device in the primary layer.

Claim 8

The process of claim 1, wherein the transition layer and the primary layer are deposited over only a portion of the surface of the silicon-on-insulator substrate, resulting in an exposed silicon surface and an exposed primary layer surface.

Claim 9

The process of claim 7, including the further step of forming a silicon-based microelectronic device in the exposed silicon portion, and forming a gallium arsenide-based microelectronic device in the primary layer.

Claim 10

A process for preparing a semiconductor heterostructure, comprising the steps of: furnishing an insulator substrate of a material selected from the group consisting of aluminum oxide and silicon dioxide; depositing a device quality silicon layer overlying the insulator substrate, said depositing including the steps of depositing a layer of silicon on the substrate, implanting ions in the layer of silicon, and regrowing the silicon layer by solid state annealing; depositing a transition layer of gallium arsenide on the device quality silicon layer, said depositing including the steps of depositing a transition layer of gallium arsenide directly on the device quality silicon layer, the transition layer of gallium arsenide having a thickness of about 200 Angstroms and being deposited at a substrate temperature of about 40° C. to about 100° C.; regrowing the transition layer of gallium arsenide by solid state annealing; and depositing a primary layer of a material selected from the group consisting of gallium arsenide and alloys thereof directly on the transition layer, by molecular beam epitaxy at a temperature of about 550° C.

Claim 11

A process for preparing a semiconductor heterostructure, comprising the steps of: furnishing an insulator substrate of a material selected from the group consisting of aluminum oxide and silicon dioxide; depositing a device quality silicon layer overlying the insulator substrate, said depositing including the steps of depositing a layer of silicon on the substrate, implanting ions in the layer of silicon, and regrowing the silicon layer by solid state annealing; depositing a transition layer of gallium arsenide on the device quality silicon layer, said depositing including the steps of depositing a transition layer of gallium arsenide directly on the device quality silicon layer, the transition layer of gallium arsenide having a thickness of about 200 Angstroms and being deposited at a substrate temperature of about 40° C. to about 100° C.; regrowing the transition layer of gallium arsenide by solid state annealing; and depositing a primary layer of a material selected from the group consisting of gallium arsenide and alloys thereof directly on the transition layer, by molecular beam epitaxy at a temperature of about 550° C.

Claim 12

The process of claim 9, including the further step of forming a microelectronic device in the primary layer.

Claim 13

The process of claim 9, wherein the transition layer and the primary layer are deposited over only a portion of the surface of the silicon-on-insulator substrate, resulting in an exposed silicon surface and an exposed primary layer surface.

Claim 14

The process of claim 11, including the further step of forming a silicon-based microelectronic device in the exposed silicon portion, and forming a gallium arsenide-based microelectronic device in the primary layer.