Temperature compensated FET power detector

Claim 2

A detector for generating an output signal representative of an input signal comprising: first detection transistor means having a control terminal for receiving the input signal, and two current-conducting terminals, one current-conducting terminal being coupled to a first reference voltage; control means for applying a control voltage on the control terminal of the first transistor means for biasing the first transistor means in a current-conducting state; first impedance means coupling the other current-conducting terminal to a second reference voltage; the first and second reference voltages being appropriate for biasing the first transistor means in a manner generating a first output signal between the first impedance means and the other current-conducting terminal representative of the input signal; and first capacitance means directly connecting the other current-conducting terminal to the first reference voltage for removing alternating current from the first output signal.

Claim 3

A detector for generating an output signal representative of an input signal comprising: first transistor means having a control terminal for receiving the input signal, and two current-conducting terminals, one current-conducting terminal being coupled to a first reference voltage; control means for applying a control voltage on the control terminal of the first transistor means for biasing the first transistor means in a current-conducting state; first impedance means coupling the other current-conducting terminal to a second reference voltage; the first and second reference voltages being appropriate for biasing the first transistor means in a manner generating a first output signal between the first impedance means and the other current-conducting terminal; first capacitance means coupling the other current-conducting terminal to the first reference voltage for removing alternating current from the first output signal; second transistor means having a control terminal coupled to the control means for receiving the control voltage, and two current-conducting terminals, one current-conducting terminal being coupled to the first reference voltage; and second impedance means coupling the other current-conducting terminal of the second transistor means to the second reference voltage; whereby a second output signal is generated between the second impedance means and the second transistor means such that the difference between the first and second output signals represents the power of the input signal.

Claim 4

A detector for generating an output signal representative of an input signal comprising: first transistor means having a control terminal for receiving the input signal, and two current-conducting terminals, one current-conducting terminal being coupled to a first reference voltage; control means for applying a control voltage on the control terminal of the first transistor means for biasing the first transistor means in a current-conducting state; first impedance means coupling the other current-conducting terminal to a second reference voltage; the first and second reference voltages being appropriate for biasing the first transistor means in a manner generating a first output signal between the first impedance means and the other current-conducting terminal; first capacitance means coupling the other current-conducting terminal to the first reference voltage for removing alternating current from the first output signal; second transistor means having a control terminal coupled to the control means for receiving the control voltage, and two current-conducting terminals, one current-conducting terminal being coupled to the first reference voltage; and second impedance means coupling the other current-conducting terminal of the second transistor means to the second reference voltage; whereby a second output signal is generated between the second impedance means and the second transistor means such that the difference between the first and second output signals represents the power of the input signal.

Claim 5

A detector according to claim 2 wherein the first impedance means comprises inductance means and resistor means coupled in series, whereby the first output signal is generated between the resistor means and the inductance means.

Claim 6

A detector according to claim 3 further comprising second capacitance means coupling the first output signal to the first reference voltage for removing alternating currents from the first output signal.

Claim 7

A detector according to claim 4 wherein the first and second transistor means vary the first and second output signals as a function of the temperature of the first and second transistor means, and the control means is responsive to the temperature of the first and second transistor means for generating the control voltage appropriately for compensating for the variation in the first and second output signals due to the variation in temperature of the first and second transistor means.

Claim 8

A detector according to claim 5 further comprising comparator means responsive to the first and second output signals for generating a third output signal representative of the difference between the first and second output signals.

Claim 9

A detector for generating an output signal representative of an input signal comprising: first transistor means having a control terminal for receiving the input signal, and two current-conducting terminals, one current-conducting terminal being coupled to a first reference voltage; control means for applying a control voltage on the control terminal of the first transistor means for biasing the first transistor means in a current-conducting state; first impedance means coupling the other current-conducting terminal to a second reference voltage; the first and second reference voltages being appropriate for biasing the first transistor means in a manner generating a first output signal between the first impedance means and the other current-conducting terminal; first capacitance means coupling the other current-conducting terminal to the first reference voltage for removing alternating current from the first output signal; the first transistor means varying the first output signal as a function of the temperature of the first transistor means, and the control means being responsive to the temperature of the first transistor means for generating the control voltage appropriately for compensating for the variation in the first output signal due to the variation in temperature of the first transistor means.

Claim 10

A detector for generating an output signal representative of an input signal comprising: first transistor means having a control terminal for receiving the input signal, and two current-conducting terminals, one current-conducting terminal being coupled to a first reference voltage; control means for applying a control voltage on the control terminal of the first transistor means for biasing the first transistor means in a current-conducting state; first impedance means coupling the other current-conducting terminal to a second reference voltage; the first and second reference voltages being appropriate for biasing the first transistor means in a manner generating a first output signal between the first impedance means and the other current-conducting terminal; first capacitance means coupling the other current-conducting terminal to the first reference voltage for removing alternating current from the first output signal; the first transistor means varying the first output signal as a function of the temperature of the first transistor means, and the control means being responsive to the temperature of the first transistor means for generating the control voltage appropriately for compensating for the variation in the first output signal due to the variation in temperature of the first transistor means.

Claim 11

A detector for generating an output signal representative of an input signal comprising: input capacitance means coupled to receive the input signal for transmitting alternating current portions of the input signal; first FET means having a gate terminal coupled to the input capacitance means for receiving only the alternating current portions of the input signal, and a source terminal connected to ground; first resistor means coupling a drain terminal of the first FET means to a positive reference voltage; first capacitance means coupling the drain terminal of the first FET means to ground for removing alternating currents from the first output signal; control means coupled to the gate terminal of the first FET means for applying a control voltage on the control terminal of the first FET means; second FET means having gate, source and drain terminals, the source terminal being coupled to ground; second resistor means coupling the drain terminal of the second FET means to the positive reference voltage; whereby the positive reference voltage is appropriate for biasing the first and second FET means in a manner generating first and second output signals between the respective drain terminals and resistor means, such that the difference between the first and second output signals represents the power of the input signal; inductance means coupled between the first resistance means and the first FET means, whereby the first output signal is generated between the first resistor means and the inductance means; second capacitance means coupling the first output signal to ground for reducing alternating currents in the first output signal; the first and second FET means varying the first and second output signals as a function of the temperature of the first and second FET means; the first and second FET means varying the first and second output signals in response to variations in the temperature of the first and second output means, and the control means being responsive to the temperature of the first and second FET means for generating the control voltage appropriately for compensating for the variation in the first and second output signals due to the variation in temperature of the first and second FET means; and comparator means responsive to the first and second output signals for generating a third output signal representative of the difference between the first and second output signals.

Claim 12

A detector for generating an output signal representative of an input signal comprising: input capacitance means coupled to receive the input signal for transmitting alternating current portions of the input signal; first FET means having a gate terminal coupled to the input capacitance means for receiving only the alternating current portions of the input signal, and a source terminal connected to ground; first resistor means coupling a drain terminal of the first FET means to a positive reference voltage; first capacitance means coupling the drain terminal of the first FET means to ground for removing alternating currents from the first output signal; control means coupled to the gate terminal of the first FET means for applying a control voltage on the control terminal of the first FET means; second FET means having gate, source and drain terminals, the source terminal being coupled to ground; second resistor means coupling the drain terminal of the second FET means to the positive reference voltage; whereby the positive reference voltage is appropriate for biasing the first and second FET means in a manner generating first and second output signals between the respective drain terminals and resistor means, such that the difference between the first and second output signals represents the power of the input signal; inductance means coupled between the first resistance means and the first FET means, whereby the first output signal is generated between the first resistor means and the inductance means; second capacitance means coupling the first output signal to ground for reducing alternating currents in the first output signal; the first and second FET means varying the first and second output signals as a function of the temperature of the first and second FET means; the first and second FET means varying the first and second output signals in response to variations in the temperature of the first and second output means, and the control means being responsive to the temperature of the first and second FET means for generating the control voltage appropriately for compensating for the variation in the first and second output signals due to the variation in temperature of the first and second FET means; and comparator means responsive to the first and second output signals for generating a third output signal representative of the difference between the first and second output signals.