US4670674A
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US
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Analog and aperiodic frequency divide-by-two circuit
Assignee: Thales SA
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Filing: 1984-02-29
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Granted: 1987-06-02
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Expires: 2004-02-29
Abstract
Abstract A frequency divide-by-two circuit capable of operating from substantially DC up to the maximum operating frequency of the component devices. First and second mixer stages receive the signal to be divided and its antiphase complement. The mixer output signals are amplified and summed. A portion of the sum signal is fed back to the other inputs of the mixers. The mixing amplifying and summing functions can all be performed by two FETs each having two gates. The divider can be integrated on a single chip since it does not make use of a filter. It can be used at frequencies of up to about 25 GHz.
Inventors
- 👤 Gerard Kantorowicz
- 👤 Didier Kaminsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:53
CPC Classifications
H; H03; H03B; H03B19/00; H03B19/06; H03B19/14; H03B21/00; H03B21/01; H03B21/02; H03B2200/00; H03B2200/003; H03B2200/0032; H03D; H03D2200/00; H03D2200/0001; H03D2200/0007
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
An analog and aperiodic frequency divide-by-two circuit for dividing a periodic signal of frequency F over a very wide range of frequencies, the divide-by-two circuit comprising: a first signal mixer for forming a product signal of a first input signal received at a first input terminal and a feedback signal received at a second input terminal wherein said first input signal is composed of a constant signal and a periodic signal of frequency F; in parallel with said first signal mixer, a second mixer for forming a product signal of a second input signal at a first input terminal and a said feedback signal at a second input terminal wherein said second input signal has a frequency F, which is complementary to said first input signal such that its periodic portion is in phase opposition with the periodic portion of said first input signal; and an amplifier-summer which has two inputs on which it receives said product signal from said first mixer and said product signal from said second mixer said amplifier-summer having an output terminal on which it supplies an output signal at the frequency F/2, a portion of the output signal being returned via a two-branched feedback loop to said mixers and being applied as said feedback signal.
Claim 2
Dependent Claim
210 words
An analog and aperiodic frequency divide-by-two circuit for dividing a periodic signal of frequency F over a very wide range of frequencies, the divide-by-two circuit comprising: a first signal mixer for forming a product signal of a first input signal received at a first input terminal and a feedback signal received at a second input terminal wherein said first input signal is composed of a constant signal and a periodic signal of frequency F; in parallel with said first signal mixer, a second mixer for forming a product signal of a second input signal at a first input terminal and a said feedback signal at a second input terminal wherein said second input signal has a frequency F, which is complementary to said first input signal such that its periodic portion is in phase opposition with the periodic portion of said first input signal; and an amplifier-summer which has two inputs on which it receives said product signal from said first mixer and said product signal from said second mixer said amplifier-summer having an output terminal on which it supplies an output signal at the frequency F/2, a portion of the output signal being returned via a two-branched feedback loop to said mixers and being applied as said feedback signal.
Claim 3
Dependent Claim
76 words
A frequency divider according to claim 1, comprising first and second two-gate field effect transistors (FETs), each of said FETs providing both the mixing and the amplifying functions in a single device, with the two gates of each FET constituting said first and second inputs for each mixer, and with the gain of each FET constituting the amplification stage and which the drains of the FETs being interconnected to provide the output terminal of the divider.
Claim 4
Dependent Claim
180 words
A frequency divider according to claim 2, comprising: said first two-gate FET having its second gate biased by a DC voltage-V G2 and also connected to receive a periodic signal of frequency F, the feedback loop of said first FET being constituted by a first impedance connected between said FET source and ground and by a second impedance connected between ground and the first gate of said first FET; said second two-gate FET having its second gate biased by a DC voltage-V G2 and also connected to receive a periodic signal of frequency F and in phase opposition to said periodic signal applied to said first FET, the feedback loop of said second FET being constituted by said first impedance conected between the second FET source and ground and by a third impedance connected between ground and the first gate of said second FET; the drains of said FETs being biased by a DC voltage V D and being interconnected to a common point which constitutes the output of the divider at which the signal at frequency F/2 is provided.
Claim 5
Dependent Claim
206 words
A frequency divider according to claim 2, comprising: said first two-gate FET having its second gate biassed by a DC voltage -V G2 and also connected to receive a periodic signal of frequency F, and having its first gate connected to ground via a first impedance, said FET having a source coupled to ground by a capacitor and being biassed by a DC voltage -V D , the feedback loop of said first FET being constituted by internal feedback between the gates and the drain thereof; said second two-gate FET having its second gate biassed by the DC voltage -V G2 and also connected to receive a periodic signal of frequency F in phase opposition to said periodic signal applied to the second gate of said first FET, and having its first gate connected to ground via a second impedance, the source of said FET being coupled to ground by a capacitor and being biassed by the DC voltage -VD, the feedback loop of said second FET beng constituted by internal feedback between the gates and the drain thereof; the drains of said FETs being interconnected to a common point which constitutes the output of the divider at which the signal at frequency F/2 is provided.
Claim 6
Dependent Claim
48 words
A divider according to claim 2, having a single stage between its input terminals and its output terminal, said single stage being constituted by said two FETs which are connected in parallel, with the maximum usable frequency of the divider being the maximum operating frequency of said FETs.
Claim 7
Dependent Claim
51 words
A frequency divider according to claim 2, wherein said FETs are Schottky gate type FETs, and wherein said feedback loop includes feedback impedances which are made by depositing respective dielectric layers on conductive layers on a substrate common to said FETs and by depositing respective conductive layers on said dielectic layers.
Claim 8
Dependent Claim
23 words
A frequency divider according to claim 6, wherein the divider is realized in integrated circuit technology on a single chip of semiconductor material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-06-01 | 1990-12-01 | 1991-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-06-01 | 1994-12-01 | 1995-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-06-01 | 1998-12-01 | 1999-06-02 | $7700.00 | Window Closed / Lapsed |