Patent US5073816A successfully refreshed from Google Patents.
US5073816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Packaging semiconductor chips
Assignee: STMicroelectronics Ltd Great Britain
•
Filing: 1990-07-25
•
Granted: 1991-12-17
•
Expires: 2010-07-25
Abstract
Abstract A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externaly of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip. The invention also relates to a method of manufacturing such a semiconductor device and to a method of assembling a semiconductor assembly.
Inventors
- 👤 Elwyn P. M. Wakefield
- 👤 Christopher P. H. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:13
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10P74/23; H10W; H10W70/00; H10W70/60; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W90/00; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
93 words
A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip.
Claim 2
Dependent Claim
93 words
A semiconductor device comprising at least one semiconductor chip, the or each semiconductor chip having a plurality of chip bonding pads, a package which encloses the at least one semiconductor chip, a first level interconnect comprising a printed circuit which overlies the at least one semiconductor chip in the package and extends externally of the package to provide a plurality of outer leads, and a second level interconnect comprising means for electrically connecting the chip bonding pads to selected contacts on the printed circuit, which contacts overlie the at least one semiconductor chip.
Claim 3
Dependent Claim
28 words
A semiconductor device according to claim 1 wherein the said electrical connection means is disposed within the area of the at least one semiconductor chip in the package.
Claim 4
Dependent Claim
23 words
A semiconductor device according to claim 1 wherein the said at least one semiconductor chip comprises a plurality of random access memories (RAMs).
Claim 5
Dependent Claim
13 words
A semiconductor device according to claim 1 wherein the printed circuit is flexible.
Claim 6
Dependent Claim
43 words
A semiconductor device according to claim 1 wherein the printed circuit comprises a plurality of electroconductive tracks extending between opposed rows of outer leads on respective opposed ends of the printed circuit, the electroconductive tracks being supported on a layer of insulating material.
Claim 7
Dependent Claim
19 words
A semiconductor device according to claim 5 wherein the electroconductive tracks are disposed between two layers of insulating material.
Claim 8
Dependent Claim
69 words
A semiconductor device according to claim 6 wherein that one of the said two layers of insulating material which is remote from the or each semiconductor chip has holes therein which reveal the said contacts which comprise bonding pads of the electroconductive tracks, and the said electrical connection means comprises a plurality of bonding wires each of which connects a respective bonding pad to a respective chip bonding pad.
Claim 9
Dependent Claim
70 words
A semiconductor device according to claim 6 wherein the contacts are comprised of a plurality of electroconductive vias of the electroconductive tracks which vias extend through that one of the said two layers of insulating material which is remote from the or each semiconductor chip, and the said electrical connection means comprises an array of electroconductive fingers each of which connects a respective via to a respective chip bonding pad.
Claim 10
Dependent Claim
20 words
A semiconductor device according to claim 8 wherein the electroconductive fingers are formed in a tape automated bonding (TAB) process.
Claim 11
Dependent Claim
126 words
A semiconductor device according to claim 5 wherein the printed circuit further comprises a second layer of insulating material which is disposed adjacent the or each semiconductor chip, the first-mentioned layer of insulating material being located over the said second layer of insulating material and the electroconductive tracks being disposed on the side of the first-mentioned layer of insulating material which is remote from the or reach chip, the contacts being comprised of a plurality of electroconductive vias of the electroconductive tracks, which vias extend through the first-mentioned layer as far as the second layer, and the said electrical connection means comprising a plurality of connectors which are disposed between the said two layers and each connect a respective via to a respective chip bonding pad.
Claim 12
Dependent Claim
27 words
A semiconductor device according to claim 1 wherein each connector carries a solder bump by means of which it is connected to the respective chip bonding pad.
References Cited (Backward Citations)
US3684818A
Cited
US4721995A
Cited
US4890152A
Cited
US4868638A
Cited
US4953005A
Cited
US5021866A
Cited
US4939570A
Cited
US4941033A
Cited
US4912547A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |