Patent US5073117A successfully refreshed from Google Patents.
US5073117A
Expired / Lapsed
US
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Flip-chip test socket adaptor and method
Assignee: Texas Instruments Inc
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Filing: 1990-12-27
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Granted: 1991-12-17
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Expires: 2010-12-27
Abstract
Abstract A test set socket adaptor (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adaptor (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate for variations in solder bumps (26) on the bare chip (22). The deflection of the cantilever beams (32) allows a positive contact between the solder bumps (26) and the cantilever beams for an AC and a burn-in test.
Inventors
- 👤 Satwinder Malhi
- 👤 Oh K. Kwon
- 👤 Shivaling S. Mahant-Shetti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:23
CPC Classifications
H; H05; H05K; H05K7/00; H05K7/02; H05K7/10; H05K7/1053; H05K7/1061; G; G01; G01R; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; G01R1/0433; G01R1/0483; G01R1/06; G01R1/067; G01R1/06711; G01R1/06716; G01R1/06727; Y; Y10; Y10S; Y10S439/00; Y10S439/912; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004; Y10T29/49117; Y10T29/49124; Y10T29/4913
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
59 words
An apparatus for providing electrical connection to integrated circuit die, comprising: a base; a support fixed to said base; and a plurality of pressure-sensitive contacts supported by said support to allow said contacts to deflect toward said base such that a die may be electrically connected to said contacts, said contacts comprising cantilever beams formed from a semiconductor material.
Claim 2
Independent Claim
59 words
An apparatus for providing electrical connection to integrated circuit die, comprising: a base; a support fixed to said base; and a plurality of pressure-sensitive contacts supported by said support to allow said contacts to deflect toward said base such that a die may be electrically connected to said contacts, said contacts comprising cantilever beams formed from a semiconductor material.
Claim 3
Dependent Claim
12 words
The apparatus of claim 1, wherein said support is 15 microns thick.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1, wherein said cantilever beams comprise a silicon material having an n type conductivity.
Claim 5
Dependent Claim
19 words
The apparatus of claim 1, wherein said contacts comprise cantilever beams formed from silicon having a p type conductivity.
Claim 6
Dependent Claim
22 words
The apparatus of claim 1, wherein said contacts further comprise solder bumps on said cantilever beams for contacting pads on the die.
Claim 7
Dependent Claim
22 words
The apparatus of claim 1, wherein said contacts further comprise pads on said cantilever beams for contacting solder bumps on the die.
Claim 8
Dependent Claim
12 words
The apparatus of claim 1, wherein said base comprises a silicon substrate.
Claim 9
Dependent Claim
14 words
The apparatus of claim 7, wherein said silicon substrate is of n type conductivity.
Claim 10
Dependent Claim
15 words
The apparatus of claim 1, wherein said support comprises silicon having a p++ type conductivity.
Claim 11
Dependent Claim
18 words
The apparatus of claim 9, wherein said support is doped up to 10 20 atoms per cubic centimeter.
Claim 12
Dependent Claim
16 words
The apparatus of claim 1, wherein said base comprises a substrate of a first conductivity type.
Claim 13
Dependent Claim
21 words
The apparatus of claim 11, wherein said support comprises semiconductor material of a second conductivity type opposite the first conductivity type.
Claim 14
Independent Claim
67 words
A method for forming an apparatus to make an electrical connection to an integrated circuit die, comprising the steps of: forming a base; forming a support over said base; and forming pressure-sensitive contacts comprising cantilever beams formed from a semiconductor material over said support to allow said contacts to deflect toward said base such that integrated circuits on the die may be electrically connected to said contacts.
Claim 15
Independent Claim
67 words
A method for forming an apparatus to make an electrical connection to an integrated circuit die, comprising the steps of: forming a base; forming a support over said base; and forming pressure-sensitive contacts comprising cantilever beams formed from a semiconductor material over said support to allow said contacts to deflect toward said base such that integrated circuits on the die may be electrically connected to said contacts.
Claim 16
Dependent Claim
21 words
The method of claim 13, wherein the step of forming a base comprises forming a layer of an n type silicon.
Claim 17
Dependent Claim
38 words
The method of claim 13, wherein the step of forming a support over said base comprises: depositing a p++ type conductivity silicon layer over said base; and selectively etching said p++ layer such that said contacts deflect therefrom.
Claim 18
Dependent Claim
32 words
The method of claim 15, wherein the step of etching comprises etching said p++ layer with an etchant comprising one part hydrochloric acid, three parts nitric acid and eight parts acetic acid.
Claim 19
Dependent Claim
59 words
The method of claim 13, wherein the step of forming contacts comprises: forming silicon over said supports; forming oxide over said silicon; forming nitride over said oxide; forming a metallic mask over said nitride; patterning said mask corresponding to said contacts; and etching said mask, said nitride, said oxide, and said silicon to form said contacts from said silicon.
Claim 20
Dependent Claim
17 words
The method of claim 17, wherein the step of etching comprises etching with a potassium hydroxide/propanol/water etchant.
Claim 21
Dependent Claim
21 words
The method of claim 13, wherein the step of forming a base comprises forming a substrate of a first conductivity type.
Claim 22
Dependent Claim
30 words
The method of claim 19, wherein the step of forming a support comprises forming a semiconductor layer of a second conductivity type opposite the first conductivity type over said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |