US4809047A
Expired / Lapsed
US
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Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short
Assignee: General Electric Co
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Filing: 1987-09-17
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Granted: 1989-02-28
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Expires: 2007-09-17
Abstract
Abstract Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-source electrode short. The implant shorting region can be formed without a specially-aligned mask by utilizing the gate electrode as an implant mask.
Inventors
- 👤 Victor A. K. Temple
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/035; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/393; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/2527; H10D64/256
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
240 words
An insulated-gate semiconductor device with an improved base-to-source electrode short, comprising: a semiconductor wafer having a substantially planar upper surface; a voltage-supporting layer of one conductivity type included in said wafer; a base region of opposite conductivity type included in said wafer, overlying said voltage-supporting layer, and having a portion extending into proximity to or to said upper surface; a source region of said one conductivity type included in said wafer and overlying said base region; a channel region included in said wafer along said base region at said upper surface and extending between said voltage-supporting layer and said source region; said substantially planar upper surface including surface portions of said voltage-supporting layer, said channel region and said source region; a gate insulatingly spaced above said channel region of said wafer, said gate having an aperture therein having a predetermined shape; a source electrode situated above said wafer and conductively coupled to said source region within the lateral confines of said aperture; and an implanted shorting region of said opposite conductivity type included in said wafer beneath said aperture adjoining both said source and base regions, having a higher conductivity than said base region, being spaced from said voltage-supporting layer and conductively coupled to said source electrode and having a dopant profile in which the region of maximum concentration of the dopant creating said implanted shorting region is within said wafer and spaced from said upper surface of said wafer.
Claim 2
Dependent Claim
240 words
An insulated-gate semiconductor device with an improved base-to-source electrode short, comprising: a semiconductor wafer having a substantially planar upper surface; a voltage-supporting layer of one conductivity type included in said wafer; a base region of opposite conductivity type included in said wafer, overlying said voltage-supporting layer, and having a portion extending into proximity to or to said upper surface; a source region of said one conductivity type included in said wafer and overlying said base region; a channel region included in said wafer along said base region at said upper surface and extending between said voltage-supporting layer and said source region; said substantially planar upper surface including surface portions of said voltage-supporting layer, said channel region and said source region; a gate insulatingly spaced above said channel region of said wafer, said gate having an aperture therein having a predetermined shape; a source electrode situated above said wafer and conductively coupled to said source region within the lateral confines of said aperture; and an implanted shorting region of said opposite conductivity type included in said wafer beneath said aperture adjoining both said source and base regions, having a higher conductivity than said base region, being spaced from said voltage-supporting layer and conductively coupled to said source electrode and having a dopant profile in which the region of maximum concentration of the dopant creating said implanted shorting region is within said wafer and spaced from said upper surface of said wafer.
Claim 3
Dependent Claim
216 words
An insulated-gate semiconductor device with an improved base-to-source electrode short, comprising: a semiconductor wafer having a substantially planar upper surface; a voltage-supporting layer of one conductivity type included in said wafer; a base region of opposite conductivity type included in said wafer atop said voltage-supporting layer, and having a portion terminating at said upper surface; a source region of said one conductivity type included in said wafer and overlying said base region; said substantially planar upper surface comprising surface portions of said voltage-supporting layer, said base region and said source region; a gate insulatingly spaced above said wafer over said surface portion of said base region, said gate having an opening therein having a predetermined shape; a source electrode situated above said wafer and conductively coupled to said source region within said opening; and an implanted shorting region of said opposite conductivity type beneath said opening and being spaced from said voltage-supporting layer, having a dopant profile in which the region of maximum concentration of the dopant creating said implanted shorting region is within said wafer and spaced from said upper surface of said wafer and exhibiting a lower concentration in proximity to said upper surface, said implanted shorting region adjoining both said source and base regions and having a higher conductivity than said base region.
Claim 4
Dependent Claim
216 words
An insulated-gate semiconductor device with an improved base-to-source electrode short, comprising: a semiconductor wafer having a substantially planar upper surface; a voltage-supporting layer of one conductivity type included in said wafer; a base region of opposite conductivity type included in said wafer atop said voltage-supporting layer, and having a portion terminating at said upper surface; a source region of said one conductivity type included in said wafer and overlying said base region; said substantially planar upper surface comprising surface portions of said voltage-supporting layer, said base region and said source region; a gate insulatingly spaced above said wafer over said surface portion of said base region, said gate having an opening therein having a predetermined shape; a source electrode situated above said wafer and conductively coupled to said source region within said opening; and an implanted shorting region of said opposite conductivity type beneath said opening and being spaced from said voltage-supporting layer, having a dopant profile in which the region of maximum concentration of the dopant creating said implanted shorting region is within said wafer and spaced from said upper surface of said wafer and exhibiting a lower concentration in proximity to said upper surface, said implanted shorting region adjoining both said source and base regions and having a higher conductivity than said base region.
Claim 5
Dependent Claim
23 words
The semiconductor device of claim 1 further comprising a conductive metal-semiconductor eutectic composition conductively interconnecting said source electrode and said implanted shorting region.
Claim 6
Dependent Claim
32 words
The semiconductor device of claim 1 wherein said source electrode adjoins said implanted shorting region and portions of said source region at respective locations beneath the plane of said wafer upper surface.
Claim 7
Dependent Claim
23 words
The semiconductor device of claim 4 wherein said source electrode further adjoins said source region at the plane of said wafer upper surface.
Claim 8
Dependent Claim
75 words
The semiconductor device of claim 1 further comprising at least one further implanted region of said opposite conductivity type included in said wafer, said at least one further implanted region having an upper surface contiguous with said wafer upper surface and a lower surface adjoining said first recited implanted shorting region, said source electrode adjoining said further implanted region at said wafer upper surface and further adjoining said source region at said wafer upper surface.
Claim 9
Dependent Claim
40 words
The semiconductor device of claim 1 further comprising a second implanted shorting region in said wafer laterally adjoining said base region and at least the major portion thereof adjoining both said first recited implanted shorting region and said voltage-supporting layer.
Claim 10
Dependent Claim
34 words
The semiconductor device of claim 7 further comprising: a minority-carrier injection region in said wafer of said opposite conductivity type and underlying said voltage-supporting layer; and a drain electrode underlying said minority-carrier injection region.
Claim 11
Dependent Claim
33 words
The semiconductor device of claim 1 wherein said source region and said voltage-supporting layer comprise seimconductor material of N-conductivity type and said base and implanted shorting regions comprise semiconductor material of P-conductivity type.
Claim 12
Dependent Claim
13 words
The semiconductor device of claim 9 wherein said wafer comprises silicon semiconductor material.
Claim 13
Dependent Claim
26 words
The insulated gate semiconductor device of claim 1 wherein said entire implanted shorting region is spaced from said substantially planar upper surface of said semiconductor wafer.
Claim 14
Dependent Claim
26 words
The insulated gate semiconductor device of claim 2 wherein said implanted shorting region is substantially parallel to said upper surface and coextensive with said source region.
Claim 15
Dependent Claim
52 words
The insulated gate semiconductor device of claim 12 wherein a first portion of said implanted shorting region includes an upper surface coplanar with the upper surface of the source region and a second portion of said implanted shorting region includes an upper surface spaced from the upper surface of the source region.
Claim 16
Dependent Claim
21 words
The insulated gate semiconductor device of claim 2 wherein said base region adjacent said surface is contiguous with said source region.
Claim 17
Dependent Claim
18 words
The insulated gate semiconductor device of claim 2 wherein said implanted region is spaced from said upper surface.
Claim 18
Dependent Claim
22 words
The insulated gate semiconductor device of claim 2 wherein said implanted region overlaps a substantial portion of said source and base regions.
Claim 19
Dependent Claim
29 words
The insulated gate semiconductor device recited in claim 1 wherein the lateral boundary of said implanted shorting region has substantially the same shape as the boundary of said aperture.
Claim 20
Dependent Claim
43 words
The insulated gate semiconductor device recited in claim 1 wherein said maximum concentration of said implanted shorting region dopant is at least an order of magnitude greater than the concentration of its dopant at said substantially planar upper surface of said semiconductor device.
Claim 21
Dependent Claim
20 words
The insulated gate semiconductor device recited in claim 1 wherein said implanted shorting region is spaced from said channel region.
Claim 22
Dependent Claim
26 words
The insulated gate semiconductor device recited in claim 6 wherein both said first recited and said further implanted shorting regions are spaced from said channel region.
Claim 23
Dependent Claim
26 words
The insulated gate semiconductor device recited in claim 7 wherein both said first recited and said second implanted shorting regions are spaced from said channel region.
Claim 24
Dependent Claim
29 words
The insulated gate semiconductor device recited in claim 2 wherein the lateral boundary of said implanted shorting region has substantially the same shape as the boundary of said opening.
Claim 25
Dependent Claim
43 words
The insulated gate semiconductor device recited in claim 2 wherein said maximum concentration of said implanted shorting region dopant is at least an order of magnitude greater than the concentration of its dopant at said substantially planar upper surface of said semiconductor device.
Claim 26
Dependent Claim
30 words
The semiconductor device of claim 1 wherein said base region, said source region and said implanted shorting region are all self aligned with respect to said aperture in said gate.
Claim 27
Dependent Claim
82 words
The semiconductor device of claim 24 wherein: said base region, said source region and said implanted shorting region each extend laterally beneath said gate from said aperture; said base region extends laterally under said gate electrode a greater distance than either said source region or said implanted shorting region; and said source region extends a greater distance laterally under said gate than said implanted shorting region and said implanted shorting region overlaps the dopant distributions which create said base and source regions.
Claim 28
Dependent Claim
57 words
The semiconductor device of claim 25 wherein said implanted shorting region is spaced from said upper surface by a portion of said source region and enhances the doping of said base region where it overlaps said base region and converts a portion of said source region where it overlaps said source region to said opposite type conductivity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |