Patent US2176255A successfully refreshed from Google Patents.
Patent US5067136A successfully refreshed from Google Patents.
US5067136A
Expired / Lapsed
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Wireless alarm system
Assignee: NORTHPEAK WIRELESS LLC
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Filing: 1990-07-12
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Granted: 1991-11-19
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Expires: 2010-07-12
Abstract
Abstract A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.
Inventors
- 👤 James D. Arthur
- 👤 H. Britton Sanderford, Jr.
- 👤 Robert E. Rouquette
- 👤 Robert J. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:38
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7073; H04B1/7075; G; G08; G08B; G08B25/00; G08B25/01; G08B25/10; H04B1/7077; H04B1/70756; H04B2201/00; H04B2201/69; H04B2201/707; H04B2201/70715
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
72 words
In a method for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver by modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by: generating a preamble for receiver chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bit sequence ranges from a one to one ratio to a ten to one ratio.
Claim 2
Dependent Claim
72 words
In a method for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver by modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by: generating a preamble for receiver chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bit sequence ranges from a one to one ratio to a ten to one ratio.
Claim 3
Dependent Claim
75 words
In an apparatus for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver comprising means for modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by: means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bid sequence ranges from a one to one ratio to a ten to one ratio.
Claim 4
Dependent Claim
75 words
In an apparatus for communicating over a communications channel using spread spectrum modulation from a transmitter to a receiver comprising means for modulating a data-bit sequence with a chip sequence having a pseudorandom chip code, the improvement characterized by: means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bid sequence ranges from a one to one ratio to a ten to one ratio.
Claim 5
Dependent Claim
193 words
A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits over a communications channel, comprising: at least one transmitter including means for generating synchronization-data bits; means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits; means using binary-phase-shift keying for modulating the carrier signal with a spread spectrum chip code; means for transmitting the carrier signal having the amplitude shift keying and binary-phase-shift keying modulation over said communications channel; at least one receiver including means responsive to the binary-phase-shift keying for demodulating the spread spectrum embedded in the carrier signal from said communications channel; and means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, a voltage threshold between the detected first voltage level and the detected second voltage level, for detecting subsequent information data bits.
Claim 6
Dependent Claim
193 words
A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits over a communications channel, comprising: at least one transmitter including means for generating synchronization-data bits; means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits; means using binary-phase-shift keying for modulating the carrier signal with a spread spectrum chip code; means for transmitting the carrier signal having the amplitude shift keying and binary-phase-shift keying modulation over said communications channel; at least one receiver including means responsive to the binary-phase-shift keying for demodulating the spread spectrum embedded in the carrier signal from said communications channel; and means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, a voltage threshold between the detected first voltage level and the detected second voltage level, for detecting subsequent information data bits.
Claim 7
Dependent Claim
50 words
The hybrid data/spread spectrum transmission system as set forth in claim 3, further comprising: means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bit sequence ranges from a one to one ratio to a ten to one ratio.
Claim 8
Dependent Claim
64 words
The hybrid data/spread spectrum transmission system as set forth in claim 3, wherein said detecting means includes detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected subsequent information-data bits, an adaptive voltage threshold between the detected first voltage level and the detected second voltage level, for detecting information data bits.
Claim 9
Dependent Claim
180 words
A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits, comprising: at least one transmitter including means for generating synchronization-data bits; means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits; means using frequency-shift keying for modulating the carrier signal with a spread spectrum chip code; means for transmitting the carrier signal having the amplitude shift keying and frequency-shift keying modulation; at least one receiver including means responsive to the frequency-shift keying for demodulating the spread spectrum embedded in the carrier signal; and means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, voltage threshold between a detected first voltage level and a detected second voltage level, for detecting subsequent information data bits.
Claim 10
Dependent Claim
180 words
A hybrid data/spread spectrum transmission system for transmitting information data bits having "1" data bits and "0" data bits, comprising: at least one transmitter including means for generating synchronization-data bits; means using amplitude shift keying having at least a first voltage level for representing the "1" data bits and a second voltage level for representing the "0" data bits, for modulating a carrier signal with the synchronization-data bits and information-data bits; means using frequency-shift keying for modulating the carrier signal with a spread spectrum chip code; means for transmitting the carrier signal having the amplitude shift keying and frequency-shift keying modulation; at least one receiver including means responsive to the frequency-shift keying for demodulating the spread spectrum embedded in the carrier signal; and means responsive to the amplitude shift keying with the synchronization-data bits for detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected synchronization-data bits, voltage threshold between a detected first voltage level and a detected second voltage level, for detecting subsequent information data bits.
Claim 11
Dependent Claim
50 words
The hybrid data/spread spectrum transmission system as set forth in claim 6, further comprising: means for generating a preamble for chip code synchronization having one of the group of alternating 1-bits and 0-bits, wherein the data-bid sequence ranges from a one to one ratio to a ten to one ratio.
Claim 12
Dependent Claim
63 words
The hybrid data/spread spectrum transmission system as set forth in claim 6, wherein said detecting means includes detecting the first voltage level and the second voltage level of the carrier signal and for determining, based on a plurality of detected information-data bits, an adaptive voltage threshold between the detected first voltage level and the detected second voltage level, for detecting information data bits.
Claim 13
Independent Claim
109 words
An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising: means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal; means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level; means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and means responsive to the second correlation voltage level being approximately equal to the first correlation voltage level for rejecting the correlation signal as noise.
Claim 14
Independent Claim
109 words
An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising: means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal; means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level; means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and means responsive to the second correlation voltage level being approximately equal to the first correlation voltage level for rejecting the correlation signal as noise.
Claim 15
Independent Claim
109 words
An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising: means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal; means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level; means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and means responsive to the second correlation voltage level being much less than the first correlation voltage level for rejecting the correlation signal as noise.
Claim 16
Independent Claim
109 words
An apparatus for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising: means for correlating the received signal with a the spread spectrum chip code to generate the correlation signal; means for searching the correlation signal for the highest correlation signal peak and measuring said highest correlation signal peak as a first correlation voltage level; means for measuring signal strength with at least one chip delay from the highest correlation signal peak as a second correlation voltage level; and means responsive to the second correlation voltage level being much less than the first correlation voltage level for rejecting the correlation signal as noise.
Claim 17
Independent Claim
108 words
A method using a processor for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising the steps, using said processor, of: correlating the received signal with a the spread spectrum chip code to generate a correlation signal; searching the correlation signal for the highest correlation signal peak; measuring said highest correlation signal peak as a first correlation voltage level; measuring signal strength with at least one chip delay from said highest correlation signal peak as a second correlation voltage level; and rejecting, in response to the second correlation voltage level being approximately equal to the first correlation voltage level, the correlation signal.
Claim 18
Independent Claim
108 words
A method using a processor for rejecting impulse noise from a received signal modulated with a spread spectrum chip code, comprising the steps, using said processor, of: correlating the received signal with a the spread spectrum chip code to generate a correlation signal; searching the correlation signal for the highest correlation signal peak; measuring said highest correlation signal peak as a first correlation voltage level; measuring signal strength with at least one chip delay from said highest correlation signal peak as a second correlation voltage level; and rejecting, in response to the second correlation voltage level being approximately equal to the first correlation voltage level, the correlation signal.
Claim 19
Dependent Claim
34 words
The method as set forth in claim 11, further including the step of: outputting in response to the second correlation voltage signal being much less than the first correlation voltage level, the correlation signal.
Claim 20
Independent Claim
111 words
An apparatus for achieving spread spectrum chip code synchronization, coupled to a receiver having an output, comprising: means coupled to said receiver output for measuring signal strength of a received signal having spread spectrum; means coupled to said measuring means, responsive to when the signal strength is above a noise floor for searching through a chip code for coarsely aligning within 1/2 chip the received signal with the chip code, and responsive to when the signal strength is below the noise floor for detecting a maximum correlation value without searching the entire chip code sequence; and means coupled to said aligning means for aligning the chip code with the received signal.
Claim 21
Independent Claim
111 words
An apparatus for achieving spread spectrum chip code synchronization, coupled to a receiver having an output, comprising: means coupled to said receiver output for measuring signal strength of a received signal having spread spectrum; means coupled to said measuring means, responsive to when the signal strength is above a noise floor for searching through a chip code for coarsely aligning within 1/2 chip the received signal with the chip code, and responsive to when the signal strength is below the noise floor for detecting a maximum correlation value without searching the entire chip code sequence; and means coupled to said aligning means for aligning the chip code with the received signal.
Claim 22
Independent Claim
107 words
A method using a processor for achieving spread spectrum chip code synchronization coupled to a receiver having an output, comprising the steps, using said processor, of: measuring signal strength of a received signal having spread spectrum; searching, in response to when the signal strength is above a noise floor, through the entire chip code sequence for coarsely aligning within 1/2 chip the received signal with the chip code; detecting, in response to when the signal strength is below the noise floor, a maximum correlation value without searching the entire chip code sequence in response to the received signal; and aligning the chip code with the received signal.
Claim 23
Independent Claim
107 words
A method using a processor for achieving spread spectrum chip code synchronization coupled to a receiver having an output, comprising the steps, using said processor, of: measuring signal strength of a received signal having spread spectrum; searching, in response to when the signal strength is above a noise floor, through the entire chip code sequence for coarsely aligning within 1/2 chip the received signal with the chip code; detecting, in response to when the signal strength is below the noise floor, a maximum correlation value without searching the entire chip code sequence in response to the received signal; and aligning the chip code with the received signal.
References Cited (Backward Citations)
US4361890A
Cited
US4193030A
Cited
US4241447A
Cited
US4351064A
Cited
US4225939A
Cited
US4317204A
Cited
US4222115A
Cited
US4255935A
Cited
US4313211A
Cited
US4360801A
Cited
US4468784A
Cited
US4392220A
Cited
US4455651A
Cited
US4418393A
Cited
US4361891A
Cited
US4400790A
Cited
US4435821A
Cited
US4387465A
Cited
US4425661A
Cited
US4511887A
Cited
US4583090A
Cited
US4517600A
Cited
US4470145A
Cited
US4472814A
Cited
US4661804A
Cited
US4484335A
Cited
US4475215A
Cited
US4550312A
Cited
US4530008A
Cited
US4594580A
Cited
US4734680A
Cited
US4728935A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-18 | 1995-05-20 | 1995-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-18 | 1999-05-20 | 1999-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-18 | 2003-05-20 | 2003-11-19 | $7700.00 | Window Closed / Lapsed |