Matched filter spread spectrum code recovery apparatus

Claim 1

Apparatus for receiving and decoding a transmitted coded message where the coded message is a modulated signal comprising a multibit data word converted into a spread spectrum code having a unique sequence of chips preceded by a sync signal and where the unique sequence of chips define a plurality of identical sequence groups each representative of said multibit data word, the combination comprising: means for receiving said sync signal and said sequence groups of chips, means for processing said sync signal and said groups of chips coupled to said receiving means to provide a time base signal and processed chips, a tapped delay line device coupled to said sync signal and said processed chips, said tapped delay line device having a chip length sufficient to accommodate one sequence group, means for detecting the output of said tapped delay line device at each chip time, means for converting the detected output of said tapped delay line device to a digital value at each chip time, shift register means coupled to said converting means being adapted to store said digital values at each chip time in the order of detection, logic means comprising a plurality of counters and maximum value detector means, said logic means being coupled to the output of said shift register means for detecting said sync signal and starting said plurality of counters, one of said counters being adapted to keep a sequence group count and another of said counters being adapted to keep a chip position count as said digital values are shifted through said shift register means, adder means connected to said converting means and to said shift register means for summing the digital value of the output of said device at each chip time with the digital value stored in said shift register means representative of the same chip time of the previously detected sequence group, and said maximum value detector means in said logic means coupled to the output of said shift register means for detecting the chip position in said sequence group having the largest digital value stored in said shift register means, whereby the largest digital value chip position in said sequence group is indicative of a unique multibit data word.

Claim 8

A method of receiving and enhancing a unique multibit data word converted into spread spectrum code form, comprising the steps of: receiving a sync signal preceding said sequence of chips and starting a sequence group count and a chip count, receiving and demodulating a plurality of unique sequence of chips representative of said multibit data word, processing said sync signal and chips in a surface acoustic wave device to generate an output at each chip time, converting the surface acoustic wave device output to a digital value, adding the digital values to a previously stored digital value representative of the same chip time within a sequence group in an adder, storing the added digital values in a shift register, recirculating the contents of said shift register back to the input of the adder to provide the previously stored digital values, repeating the step of adding the digital values to a previously stored digital value a predetermined number of times, and detecting the chip position in said sequence group indicative of the largest digital value stored where the unique chip position is indicative of said unique multibit data word.

Claim 9

A method of receiving and enhancing a unique multibit data word converted into spread spectrum code form, comprising the steps of: receiving a sync signal preceding said sequence of chips and starting a sequence group count and a chip count, receiving and demodulating a plurality of unique sequence of chips representative of said multibit data word, processing said sync signal and chips in a surface acoustic wave device to generate an output at each chip time, converting the surface acoustic wave device output to a digital value, adding the digital values to a previously stored digital value representative of the same chip time within a sequence group in an adder, storing the added digital values in a shift register, recirculating the contents of said shift register back to the input of the adder to provide the previously stored digital values, repeating the step of adding the digital values to a previously stored digital value a predetermined number of times, and detecting the chip position in said sequence group indicative of the largest digital value stored where the unique chip position is indicative of said unique multibit data word.