Amorphous silicon thin film transistor array substrate and method for producing the same

Claim 2

In an amorphous silicon thin film transistor array substrate having an array region and a connecting region outside of said array region, and comprising: a plurality of amorphous silicon thin film transistors formed on an insulating substrate and having a gate insulating layer, all of said amorphous silicon thin film transistors being formed inside said array region, a gate wiring connecting gate electrodes of said amorphous silicon thin film transistor array to one another, a gate terminal connected to said gate wiring and adapted to be connected to external wiring, a source wiring connecting source electrodes of said amorphous silicon thin film transistors to one another, and a source terminal of given area connected to said source wiring and adapted to be connected to external wiring, said source terminal being formed entirely inside of said connecting region, the improvement wherein said gate insulating layer extends between said source terminal and said insulating substrate and spaces the entire area of said source terminal from said substrate.

Claim 3

An amorphous silicon thin film transistor array substrate comprising: a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and a source and a drain electrode formed on said amorphous silicon layer, said gate insulating layer covering the gate electrodes and most of the gate wiring, and being formed on substantially the entire surface of said insulating substrate, said gate wiring connecting said gate electrodes to one another, and a gate terminal adjacent an edge of said insulating substrate and connected to said gate wiring, said gate terminal being adapted to be connected to an external circuit, said gate wiring being covered by said gate insulating layer, said gate terminal being free of covering by said gate insulating layer, and a source wiring connecting said source electrodes to one another, and a source terminal adjacent an edge of said insulating substrate and connected to said source wiring, for connection to an external circuit, said source wiring and said source terminal being formed entirely on said gate insulating layer, whereby said source terminal is at the same level as the portions of the source wiring adjacent thereto.

Claim 4

An amorphous silicon thin film transistor array substrate comprising: a plurality of amorphous silicon thin film transistors formed on an insulating substrate, each of said amorphous silicon thin film transistors having a gate electrode formed on said insulating substrate, a gate insulating layer covering said gate electrode, an amorphous silicon layer formed on said gate insulating layer, and a source and a drain electrode formed on said amorphous silicon layer, said gate insulating layer covering the gate electrodes and most of the gate wiring, and being formed on substantially the entire surface of said insulating substrate, said gate wiring connecting said gate electrodes to one another, and a gate terminal adjacent an edge of said insulating substrate and connected to said gate wiring, said gate terminal being adapted to be connected to an external circuit, said gate wiring being covered by said gate insulating layer, said gate terminal being free of covering by said gate insulating layer, and a source wiring connecting said source electrodes to one another, and a source terminal adjacent an edge of said insulating substrate and connected to said source wiring, for connection to an external circuit, said source wiring and said source terminal being formed entirely on said gate insulating layer, whereby said source terminal is at the same level as the portions of the source wiring adjacent thereto.

Claim 5

In an amorphous silicon thin film transistor array formed on an insulating substrate and having a gate insulating layer, a gate wiring connecting gate electrodes of said amorphous silicon thin film transistor array to one another, a gate terminal connected to said gate wiring and adapted to be connected to external wiring, source wiring connecting source electrodes to one another, and a source terminal connected to said source wiring for enabling external connection to said source wiring, the improvement wherein said gate insulating layer extends between said source terminal and said insulating substrate to space all of said source terminal from said substrate, whereby said source terminal extends at the same level as the portion of said source wiring connected thereto.

Claim 6

In an amorphous silicon thin film transistor array formed on an insulating substrate and having a gate insulating layer, a gate wiring connecting gate electrodes of said amorphous silicon thin film transistor array to one another, a gate terminal connected to said gate wiring and adapted to be connected to external wiring, source wiring connecting source electrodes to one another, and a source terminal connected to said source wiring for enabling external connection to said source wiring, the improvement wherein said gate insulating layer extends between said source terminal and said insulating substrate to space all of said source terminal from said substrate, whereby said source terminal extends at the same level as the portion of said source wiring connected thereto.