Arbiter circuit using plural-reset rs flip-flops

Claim 2

An arbiter circuit comprising: (a) a first latch circuit to which a first request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said first request signal is supplied and a reset input terminal to which a first reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least three reset input terminals; (b) a second latch circuit to which a second request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said second request signal is supplied and a reset input terminal to which a second reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least two reset input terminals; (c) means for controlling the transmission of signals from said input stage RS flip-flops of said first and second latch circuits to said set input terminals of said output stage RS flip-flops, according to signals of said first output terminals of said output stage flip-flops of said first and second latch circuits; (d) means for feeding said signal of said first output terminal of said output stage RS flip-flop of said second latch circuit to a first reset input terminal of said output stage RS flip-flop of said first latch circuit; (e) a first delay circuit connected between said second output terminal and a second reset input terminal, of said output stage RS flip-flop of said first latch circuit; (f) a second delay circuit connected between said second output terminal and a first reset input terminal, of said output stage RS flip-flop of said second latch circuit; and (g) means for feeding a common reset signal to a third reset input terminal of said output stage RS flip-flop of said first latch circuit, and a second reset input terminal of said output stage RS flip-flop of said second latch circuit.

Claim 3

An arbiter circuit according to claim 1, wherein the delay time of said first and second delay circuits is set longer than the delay time from the supply of signals to said set input terminals of said output stage RS flip-flops of said first and second latch circuits until said signals are latched in said first and second output terminals of said output stage RS flip-flops.

Claim 4

An arbiter circuit according to claim 1, wherein said first and second request signals are a write request and a read request signal in a dynamic random access memory device.

Claim 5

An arbiter circuit comprising: (a) a first latch circuit to which a first request signal is supplied, said first latch circuit containing an input stage RS flip-flop possessing a set input terminal to which said first request signal is supplied and a reset input terminal to which a first reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least four reset input terminals; (b) a second latch circuit to which a second request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said second request signal is supplied and a reset input terminal to which a second reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least three reset input terminals; (c) a third latch circuit to which a third request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said third request signal is supplied and a reset input terminal to which a third reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least two reset input terminals; (d) means for controlling the transmission of signals from said input stage RS flip-flops of said first, second and third latch circuits to said set input terminals of said output stage RS flip-flops, according to signals of said first output terminals of said output stage RS flip-flops of said first, second and third latch circuits; (e) means for feeding said signal of said first output terminal of said output stage RS flip-flop of said second latch circuit to a first reset input terminal of said output stage RS flip-flop of said first latch circuit; (f) means for feeding said signal of said first output terminal of said output stage RS flip-flop of said third latch circuit to said second reset terminal of said output stage RS flip-flop of said first latch circuit and a first reset input terminal of said output RS flip-flop of said second latch circuit; (g) a first delay circuit connected between said second output terminal and a third reset input terminal of said output stage RS flip-flop of said first latch circuit; (h) a second delay circuit connected between said second output terminal and a second reset input terminal of said output stage RS flip-flop of said second latch circuit; (i) a third delay circuit connected between said second output terminal and a first reset input terminal of said output stage RS flip-flop of said third latch circuit; and (j) means for feeding a common reset signal to a fourth reset input terminal of said output stage RS flip-flop of said first latch circuit, a third reset input terminal of said output stage RS flip-flop of said second latch circuit, and a second reset input terminal of said third latch circuit.

Claim 6

An arbiter circuit comprising: (a) a first latch circuit to which a first request signal is supplied, said first latch circuit containing an input stage RS flip-flop possessing a set input terminal to which said first request signal is supplied and a reset input terminal to which a first reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least four reset input terminals; (b) a second latch circuit to which a second request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said second request signal is supplied and a reset input terminal to which a second reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least three reset input terminals; (c) a third latch circuit to which a third request signal is supplied, containing an input stage RS flip-flop possessing a set input terminal to which said third request signal is supplied and a reset input terminal to which a third reset signal is supplied, and an output stage RS flip-flop possessing a set input terminal, first and second output terminals and at least two reset input terminals; (d) means for controlling the transmission of signals from said input stage RS flip-flops of said first, second and third latch circuits to said set input terminals of said output stage RS flip-flops, according to signals of said first output terminals of said output stage RS flip-flops of said first, second and third latch circuits; (e) means for feeding said signal of said first output terminal of said output stage RS flip-flop of said second latch circuit to a first reset input terminal of said output stage RS flip-flop of said first latch circuit; (f) means for feeding said signal of said first output terminal of said output stage RS flip-flop of said third latch circuit to said second reset terminal of said output stage RS flip-flop of said first latch circuit and a first reset input terminal of said output RS flip-flop of said second latch circuit; (g) a first delay circuit connected between said second output terminal and a third reset input terminal of said output stage RS flip-flop of said first latch circuit; (h) a second delay circuit connected between said second output terminal and a second reset input terminal of said output stage RS flip-flop of said second latch circuit; (i) a third delay circuit connected between said second output terminal and a first reset input terminal of said output stage RS flip-flop of said third latch circuit; and (j) means for feeding a common reset signal to a fourth reset input terminal of said output stage RS flip-flop of said first latch circuit, a third reset input terminal of said output stage RS flip-flop of said second latch circuit, and a second reset input terminal of said third latch circuit.

Claim 7

An arbiter circuit according to claim 4, wherein the delay time of said first, second and third delay circuits is set longer than the delay time from the supply of signals to said set input terminals of said output stage RS flip-flops of said first, second, and third latch circuits until said signals are latched in said first and second output terminals of said output stage RS flip-flops.

Claim 8

An arbiter circuit according to claim 4, wherein any one of said first, second and third request signals is a write request signal, another one is a read request signal, and the other one is a refresh request signal of a dynamic random access memory device.

Claim 9

An arbiter circuit comprising: (a) plural latch circuits and plural request signals in the same number, each latch circuit of said plural latch circuits containing an input stage RS flip-flop possessing a set input terminal to which said request signal is supplied, and a reset input terminal to which a reset signal is supplied, and an output signal RS flip flop possessing a set input terminal, first and second output terminals and plural reset input terminals; (b) means for controlling the transmission of signals from said input stage RS flip-flops to said set input terminals of said output stage RS flip-flops of said latch circuits, according to signals of said first output terminals of said output stage RS flip-flops of said latch circuits; (c) means for feeding said signal of said first output terminal of said output stage RS flip-flop of a specified latch circuit out of said plural latch circuit, to a reset input terminal of said output stage RS flip-flop of the other latch circuit; (d) plural delay circuits connected between said second output terminal and a reset input terminal of each said output stage RS flip-flop, respectively; and (e) means for feeding a common reset signal to the other reset input terminals of said output stage RS flip-flops.

Claim 10

An arbiter circuit comprising: (a) plural latch circuits and plural request signals in the same number, each latch circuit of said plural latch circuits containing an input stage RS flip-flop possessing a set input terminal to which said request signal is supplied, and a reset input terminal to which a reset signal is supplied, and an output signal RS flip flop possessing a set input terminal, first and second output terminals and plural reset input terminals; (b) means for controlling the transmission of signals from said input stage RS flip-flops to said set input terminals of said output stage RS flip-flops of said latch circuits, according to signals of said first output terminals of said output stage RS flip-flops of said latch circuits; (c) means for feeding said signal of said first output terminal of said output stage RS flip-flop of a specified latch circuit out of said plural latch circuit, to a reset input terminal of said output stage RS flip-flop of the other latch circuit; (d) plural delay circuits connected between said second output terminal and a reset input terminal of each said output stage RS flip-flop, respectively; and (e) means for feeding a common reset signal to the other reset input terminals of said output stage RS flip-flops.

Claim 11

An arbiter circuit according to claim 7, wherein the delay time of said delay circuits is set longer than the delay time from the supply of signals to said set input terminals of said output stage RS flip-flops until said signals are latched in said first and second output terminals of said output stage RS flip-flops.