US4918664A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for preserving data integrity in multiple-port RAMS
Assignee: Cypress Semiconductor Corp
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Filing: 1989-01-18
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Granted: 1990-04-17
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Expires: 2009-01-18
Abstract
Abstract The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second address transition signals to enable data storage in a single memory address. A comparator is coupled to the first and second ports (1) for detecting address transitions indicating that the second port is addressing a particular memory address coincidentally when the first port also is addressing the same memory address, and (2) for generating a busy output signal for that address in the event of such coincidence. A transition detection circuit is used to detect the transition resulting from the removal of the busy output signal from the comparator and for providing a busy removal output signal equivalent to an address detection signal in the event of such detection. Finally, the busy removal output signal is combined with the transition detection signals, whereby the data from the second port may be written into the single memory address irrespective of whether the second port itself provides an address transition signal at that time.
Inventors
- 👤 Paul E. Platt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:21
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
213 words
In a random access memory having more than one port capable of accessing the same storage addresses, a system for protection of data integrity at each port comprising: first and second ports capable of providing first and second address transition signals to enable data storage in a single memory address; a comparator means coupled to said first and second ports (1) for detecting address transitions indicating that said second port is addressing a particular memory address coincidentally when said first port is addressing the same memory address and for (2) generating a busy output signal for that address in the event of such coincidence; a transition detection means for detecting the transition resulting from the removal of said busy output signal from said comparator and for providing a busy removal transition signal equivalent to an address detection signal in the event of such detection; and means for logically ORing said busy removal transition signal from said transition detection means with the address transition signal from said second port, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal at that time.
Claim 2
Dependent Claim
213 words
In a random access memory having more than one port capable of accessing the same storage addresses, a system for protection of data integrity at each port comprising: first and second ports capable of providing first and second address transition signals to enable data storage in a single memory address; a comparator means coupled to said first and second ports (1) for detecting address transitions indicating that said second port is addressing a particular memory address coincidentally when said first port is addressing the same memory address and for (2) generating a busy output signal for that address in the event of such coincidence; a transition detection means for detecting the transition resulting from the removal of said busy output signal from said comparator and for providing a busy removal transition signal equivalent to an address detection signal in the event of such detection; and means for logically ORing said busy removal transition signal from said transition detection means with the address transition signal from said second port, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal at that time.
Claim 3
Dependent Claim
212 words
In a random access memory having more than one port capable of accessing the same storage addresses, a system for protection of data integrity at each port comprising: first and second ports capable of providing first and second address transition signals to enable data storage in a single memory address: sense line means for logically ORing the address transition signals from said second port; a comparator means coupled to said first and second ports (1) for detecting address transitions indicating that said second port is addressing a particular memory address coincidentally when said first port is addressing the same memory address and for (2) generating a busy output signal for that address in the event of such coincidence; and a transition detection means for detecting the transition resulting from the removal of said busy output signal from said comparator and for providing a busy removal transition signal equivalent to an address transition signal to said sense line in the event of such detection, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal to said sense line at that time.
Claim 4
Dependent Claim
212 words
In a random access memory having more than one port capable of accessing the same storage addresses, a system for protection of data integrity at each port comprising: first and second ports capable of providing first and second address transition signals to enable data storage in a single memory address: sense line means for logically ORing the address transition signals from said second port; a comparator means coupled to said first and second ports (1) for detecting address transitions indicating that said second port is addressing a particular memory address coincidentally when said first port is addressing the same memory address and for (2) generating a busy output signal for that address in the event of such coincidence; and a transition detection means for detecting the transition resulting from the removal of said busy output signal from said comparator and for providing a busy removal transition signal equivalent to an address transition signal to said sense line in the event of such detection, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal to said sense line at that time.
Claim 5
Dependent Claim
24 words
The random access memory of claim 2 wherein each port has associated sense line means for combining the address transition signals at that port.
Claim 6
Dependent Claim
191 words
In a random access memory having more than one port capable of accessing the same storage addresses, the method of protecting data integrity at each port comprising; providing first and second address transition signals to two separate ports to enable data storage in a single memory address; detecting coincident address transitions from said first and second ports indicating that said second port is addressing a particular memory address while said first port is addressing the same memory address; generating a busy output signal for said particular memory address in the event of detection of such coincidence; detecting the transition resulting from the completion of said busy output signal from said comparator; providing a busy removal output signal equivalent to an address detection signal in the event of such detection; and logically ORing said busy removal transition signal with the address transition signals from said second port, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal at that time.
Claim 7
Dependent Claim
191 words
In a random access memory having more than one port capable of accessing the same storage addresses, the method of protecting data integrity at each port comprising; providing first and second address transition signals to two separate ports to enable data storage in a single memory address; detecting coincident address transitions from said first and second ports indicating that said second port is addressing a particular memory address while said first port is addressing the same memory address; generating a busy output signal for said particular memory address in the event of detection of such coincidence; detecting the transition resulting from the completion of said busy output signal from said comparator; providing a busy removal output signal equivalent to an address detection signal in the event of such detection; and logically ORing said busy removal transition signal with the address transition signals from said second port, whereby, in response to an output from said combining means, the data from said second port may then be written into or read out of said single memory address irrespective of whether said second port itself is providing an address transition signal at that time.
References Cited (Backward Citations)
US4742493A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |