US4998027A
Expired / Lapsed
US
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Arbiter circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1990-03-09
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Granted: 1991-03-05
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Expires: 2010-03-09
Abstract
Abstract Disclosed is an arbiter circuit for arbitrating a contention between two request signals which simultaneously attain the H (logical high) level indicating a "request". In this arbiter circuit, buffer circuits, having different input logic threshold voltages, are connected to the respective outputs of two three-input NAND gates. The respective outputs of these two buffer circuits, as signals indicating "acknowledgement" or "negative acknowledgement" of the request signals, are derived as final outputs of the arbiter circuit. One of the buffer circuits has an input logic threshold voltage lower than a logic threshold voltage of the two NAND gates, while the other buffer circuit has an input logic threshold voltage set higher than the logic threshold voltage of the NAND gates. Therefore, when the NAND gates output a voltage with the logic level neither the H level nor the L (logical low) level, a signal of the logic level H indicating the "negative acknowledgement" and a signal of the logical level L indicating the "acknowledgement" are reliably outputted from the buffer circuit with the lower input logic threshold voltage and from the other buffer circuit with the higher input logic threshold voltage, respectively. That is, even if two requests occur simultaneously, one of the request signals is rapidly acknowledged.
Inventors
- 👤 Masaaki Mihara
- 👤 Toshifumi Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
359 words
An arbiter circuit comprising: first logic means for receiving a first request signal; second logic means for receiving a second request signal; first buffer means for receiving an output signal from said first logic means; and second buffer means for receiving an output signal from said second logic means, said first logic means being connected to receive the output signal from said second logic means and an output signal from said second buffer means, said second logic means being connected to receive the output signal from said first logic means and an output signal from said first buffer means, said first logic means, when receiving said first request signal earlier than when said second logic means receives said second request signal, outputting a first signal of a first logic level indicating acknowledgment of said first request signal as received, said second logic means, when receiving said second request signal earlier than when said first logic means receives said first request signal, outputting a second signal of a first logic level indicating acknowledgment of said second request signal as received, said second logic means, even if receiving said second request signal while said first signal of said first logic level is being outputted from said first logic means, outputting a signal of a second logic level different from the first logic level indicating negative acknowledgment of said second request signal as received, said first logic means, even if receiving said first request signal while said second signal of said first logic level is being outputted from said second logic means, outputting a signal of a second logic level different from the first logic level indicating negative acknowledgement of said first request signal as received, said first and second logic means each outputting a signal of a third level intermediate between the first and second logic levels when simultaneously receiving said first and second request signals, respectively, said first buffer means providing said signal of the first logic level in response to said signal of the third logic level, said second buffer means outputting said signal of the second logic level in response to said signal of the third logic level.
Claim 2
Dependent Claim
359 words
An arbiter circuit comprising: first logic means for receiving a first request signal; second logic means for receiving a second request signal; first buffer means for receiving an output signal from said first logic means; and second buffer means for receiving an output signal from said second logic means, said first logic means being connected to receive the output signal from said second logic means and an output signal from said second buffer means, said second logic means being connected to receive the output signal from said first logic means and an output signal from said first buffer means, said first logic means, when receiving said first request signal earlier than when said second logic means receives said second request signal, outputting a first signal of a first logic level indicating acknowledgment of said first request signal as received, said second logic means, when receiving said second request signal earlier than when said first logic means receives said first request signal, outputting a second signal of a first logic level indicating acknowledgment of said second request signal as received, said second logic means, even if receiving said second request signal while said first signal of said first logic level is being outputted from said first logic means, outputting a signal of a second logic level different from the first logic level indicating negative acknowledgment of said second request signal as received, said first logic means, even if receiving said first request signal while said second signal of said first logic level is being outputted from said second logic means, outputting a signal of a second logic level different from the first logic level indicating negative acknowledgement of said first request signal as received, said first and second logic means each outputting a signal of a third level intermediate between the first and second logic levels when simultaneously receiving said first and second request signals, respectively, said first buffer means providing said signal of the first logic level in response to said signal of the third logic level, said second buffer means outputting said signal of the second logic level in response to said signal of the third logic level.
Claim 3
Dependent Claim
28 words
An arbiter circuit in accordance with claim 1, wherein an input logic threshold voltage of said first buffer means is lower than that of said second buffer means.
Claim 4
Dependent Claim
28 words
An arbiter circuit in accordance with claim 1 wherein said first logic means comprises a first NAND gate, and said second logic means comprises a second NAND gate.
Claim 5
Dependent Claim
54 words
An arbiter circuit in accordance with claim 3, wherein the input logic threshold voltage of said first buffer means is lower than a logic threshold voltage of said first logic means, and the input logic threshold voltage of said second buffer means is higher than a logic threshold voltage of said second logic means.
Claim 6
Dependent Claim
23 words
An arbiter circuit in accordance with claim 1, wherein each of said first and second buffer circuits comprises two inverters connected in series.
Claim 7
Dependent Claim
332 words
An arbiter circuit comprising: a first three-input NAND gate receiving a first request signal with one logic level; a second three-input NAND gate receiving a second request signal with said one logic level; a first buffer circuit receiving an output of said first NAND gate and having a first input logic threshold voltage; and a second buffer circuit receiving an output of said second NAND gate and having a second input logic threshold voltage higher than said first input logic threshold voltage, said first NAND gate being connected to receive the output of said second NAND gate and an output of said second buffer circuit, said second NAND gate being connected to receive the output of said first NAND gate and an output of said first buffer circuit, said first and second NAND gates both having the same logic threshold voltage between said first and second input logic threshold voltages, said first buffer circuit outputting, as a signal indicating acknowledgement of said first request signal, a voltage of a first logic level when the output voltage of said first NAND gate is lower than said first input logic threshold voltage, and outputting, as a signal indicating negative acknowledgement of said first request signal, a voltage of a second logic level when the output voltage of said first NAND gate is higher than said first input logic threshold voltage, said second buffer circuit outputting, as a signal indicating acknowledgement of said second request signal, a voltage of a first logic level when the output voltage of said second NAND gate is lower than said second input logic threshold voltage, and outputting, as a signal indicating negative acknowledgement of said second request signal, a voltage of a second logic level when the output voltage of said second NAND gate is higher than said second input logic threshold voltage, said first and second NAND gates each outputting a voltage equal to said logic threshold voltage when simultaneously receiving said first and second request signals, respectively.
Claim 8
Dependent Claim
332 words
An arbiter circuit comprising: a first three-input NAND gate receiving a first request signal with one logic level; a second three-input NAND gate receiving a second request signal with said one logic level; a first buffer circuit receiving an output of said first NAND gate and having a first input logic threshold voltage; and a second buffer circuit receiving an output of said second NAND gate and having a second input logic threshold voltage higher than said first input logic threshold voltage, said first NAND gate being connected to receive the output of said second NAND gate and an output of said second buffer circuit, said second NAND gate being connected to receive the output of said first NAND gate and an output of said first buffer circuit, said first and second NAND gates both having the same logic threshold voltage between said first and second input logic threshold voltages, said first buffer circuit outputting, as a signal indicating acknowledgement of said first request signal, a voltage of a first logic level when the output voltage of said first NAND gate is lower than said first input logic threshold voltage, and outputting, as a signal indicating negative acknowledgement of said first request signal, a voltage of a second logic level when the output voltage of said first NAND gate is higher than said first input logic threshold voltage, said second buffer circuit outputting, as a signal indicating acknowledgement of said second request signal, a voltage of a first logic level when the output voltage of said second NAND gate is lower than said second input logic threshold voltage, and outputting, as a signal indicating negative acknowledgement of said second request signal, a voltage of a second logic level when the output voltage of said second NAND gate is higher than said second input logic threshold voltage, said first and second NAND gates each outputting a voltage equal to said logic threshold voltage when simultaneously receiving said first and second request signals, respectively.
Claim 9
Dependent Claim
62 words
An arbiter circuit in accordance with claim 6, wherein said one logic level is the logically high level; the first logic level of said signal indicating acknowledgement of said first and second request signals is the logically low level; and the second logic level of said signal indicating negative acknowledgement of said first and second request signals is the logically high level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-04 | 1994-09-03 | 1995-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-04 | 1998-09-03 | 1999-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-04 | 2002-09-03 | 2003-03-05 | $7700.00 | Window Closed / Lapsed |