Patent US5065043A successfully refreshed from Google Patents.
US5065043A
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US
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Biasing circuits for field effect transistors using GaAs FETS
Assignee: Texas Instruments Inc
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Filing: 1990-03-09
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Granted: 1991-11-12
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Expires: 2010-03-09
Abstract
Abstract Hysteresis effects in low frequency field effect transistor circuits are minimized by using biasing or clamping circuits including field effect transistors.
Inventors
- 👤 James E. Bartling
- 👤 Dale A. Heaton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:25
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45376; H03F3/45381; H03F3/45385; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; H03F1/00; H03F1/08; H03F1/22; H03F1/226
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
100 words
A circuit for minimizing the changes in transistor biasing over all frequencies, including field effect transistors having source, drain and gate connections, comprising; a first field effect transistor circuit having source drain and gate connections; and a second GaAs field effect transistor circuit having gate and source connections, said second GaAs field effect transistor circuit with gate and source connections connected across the source and drain connections of the first field effect transistor respectively; wherein the second field effect transistor controls the bias of the first field effect transistor by sensing the voltage at source connection of the first transistor.
Claim 2
Dependent Claim
100 words
A circuit for minimizing the changes in transistor biasing over all frequencies, including field effect transistors having source, drain and gate connections, comprising; a first field effect transistor circuit having source drain and gate connections; and a second GaAs field effect transistor circuit having gate and source connections, said second GaAs field effect transistor circuit with gate and source connections connected across the source and drain connections of the first field effect transistor respectively; wherein the second field effect transistor controls the bias of the first field effect transistor by sensing the voltage at source connection of the first transistor.
Claim 3
Dependent Claim
140 words
A circuit for minimizing the changes in transistor biasing over all frequencies, including field effect transistors having source, drain and gate connections, connected as a differential amplifier comprising; a first field effect transistor having gate, source and drain connections; a second field effect transistor having gate, source and drain connections; a first bias control GaAs field effect transistor connected between the source and drain of the first field effect transistor; and a second bias control GaAs field effect transistor connected between the source and drain of the second field effect transistor; the gate connections of the first and second bias control GaAs field effect transistors are connected together and to the source connections of the first and second field effect transistors; and the gate connections of the first and second field effect transistors serving as inputs for the differential amplifier.
Claim 4
Dependent Claim
140 words
A circuit for minimizing the changes in transistor biasing over all frequencies, including field effect transistors having source, drain and gate connections, connected as a differential amplifier comprising; a first field effect transistor having gate, source and drain connections; a second field effect transistor having gate, source and drain connections; a first bias control GaAs field effect transistor connected between the source and drain of the first field effect transistor; and a second bias control GaAs field effect transistor connected between the source and drain of the second field effect transistor; the gate connections of the first and second bias control GaAs field effect transistors are connected together and to the source connections of the first and second field effect transistors; and the gate connections of the first and second field effect transistors serving as inputs for the differential amplifier.
Claim 5
Dependent Claim
28 words
The circuit according to claim 2, wherein the output of the differential amplifier is across the drain connections of said first and second bias GaAs field effect transistors.
Claim 6
Dependent Claim
29 words
The circuit according to claim 2, including first and second buffer circuits connected to the first and second gate connections, respectively, of said first and second field effect circuits.
Claim 7
Dependent Claim
16 words
The circuit according to claim 4, wherein said buffer circuits are gate to source follower circuits.
Claim 8
Dependent Claim
30 words
The circuit according to claim 4, wherein the buffer circuits include series connected field effect transistors having the gate of each of the series connected field effect transistors connected together.
Claim 9
Dependent Claim
87 words
A biasing circuit for minimizing the changes in field effect transistor biasing over all frequencies, each field effect transistor having source, drain and gate connections including: a bias control GaAs field effect transistor having gate and source connections connected to a second field effect transistor such that the bias control GaAs field effect transistor gate and source connections are connected between the source and drain of the second field effect transistor respectively; wherein the bias control transistor has a gate to source voltage of approximately zero volt.
Claim 10
Dependent Claim
87 words
A biasing circuit for minimizing the changes in field effect transistor biasing over all frequencies, each field effect transistor having source, drain and gate connections including: a bias control GaAs field effect transistor having gate and source connections connected to a second field effect transistor such that the bias control GaAs field effect transistor gate and source connections are connected between the source and drain of the second field effect transistor respectively; wherein the bias control transistor has a gate to source voltage of approximately zero volt.
Claim 11
Dependent Claim
29 words
The biasing circuit according to claim 7, wherein the I DSS of the bias control GaAs transistor is approximately twice the I DSS of the second field effect transistor.
Claim 12
Dependent Claim
15 words
The method according to claim 7, wherein the second transistor is a gallium arsenide transistor.
Claim 13
Dependent Claim
127 words
Biasing and buffer circuits for a differential circuit including two input field effect transistors, said differential amplifier and biasing/buffer circuit comprising: a first field effect transistor having gate, source and drain connections; a second field effect transistor having gate, source and drain connections; a first bias control GaAs field effect transistor connected between the source and drain of the first field effect transistor; a second bias control GaAs field effect transistor connected between the source and drain of the second field effect transistor; the source connections of the first and second field effect transistors are connected together; and the gate connections of the first and second bias GaAs field effect transistors are connected together and to the source connections of the first and second field effect transistors.
Claim 14
Dependent Claim
127 words
Biasing and buffer circuits for a differential circuit including two input field effect transistors, said differential amplifier and biasing/buffer circuit comprising: a first field effect transistor having gate, source and drain connections; a second field effect transistor having gate, source and drain connections; a first bias control GaAs field effect transistor connected between the source and drain of the first field effect transistor; a second bias control GaAs field effect transistor connected between the source and drain of the second field effect transistor; the source connections of the first and second field effect transistors are connected together; and the gate connections of the first and second bias GaAs field effect transistors are connected together and to the source connections of the first and second field effect transistors.
Claim 15
Dependent Claim
28 words
The circuit according to claim 10, wherein the output of the differential circuit is across the drain connections of said first and second bias GaAs field effect transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-11 | 1995-05-13 | 1995-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-11 | 1999-05-13 | 1999-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-11 | 2003-05-13 | 2003-11-12 | $7700.00 | Window Closed / Lapsed |