Abstract This present invention provides a voltage sustainer which eliminates the DC current problems of conventional voltage sustainers. The embodiment of the voltage sustainer of the present invention comprises a first field effect transistor (FET) having its drain connected to a supply voltage and its drain connected to a second FET; a second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; a third FET having its source connected to the gate of the second FET and its drain connected to the output node; a first MOS capacitor having one side connected to receive an input signal and its other side connected to the interconnection between the source of the first FET and the drain of the second FET; and a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.
A circuit for sustaining a preselected voltage level, the circuit comprising: (a) a first field effect transistor (FET) having its drain connected to a supply voltage and its source connected to a second FET; (b) said second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; (c) said third FET having its source connected to the gate of the second FET and its drain connected to the output node; (d) a first capacitor having one side connected to receive an input signal and its second side connected to the interconnection between the source of the first FET and the drain of the second FET; and (e) a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.
Claim 2
Dependent Claim
151 words
A circuit for sustaining a preselected voltage level, the circuit comprising: (a) a first field effect transistor (FET) having its drain connected to a supply voltage and its source connected to a second FET; (b) said second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; (c) said third FET having its source connected to the gate of the second FET and its drain connected to the output node; (d) a first capacitor having one side connected to receive an input signal and its second side connected to the interconnection between the source of the first FET and the drain of the second FET; and (e) a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.