US5063537A
Expired / Lapsed
US
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Reprogrammable logic fuse based on a 6-device sram cell for logic arrays
Assignee: International Business Machines Corp
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Filing: 1989-09-29
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Granted: 1991-11-05
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Expires: 2009-09-29
Abstract
Abstract A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs). In the latter case, in the AND array the input and output lines are respectively the product term lines (if bit partitioning is employed) and AND term lines (or Match Lines). In the OR array, the input and output lines are respectively the Match Out lines (the signal on the Match Line after complementation) and the OR out lines. RPLAs employing these RLF's can be dynamically reprogrammed to allow in system logical reconfiguration in real time.
Inventors
- 👤 Chekib Akrout
- 👤 Pierre Coppens
- 👤 Yves Gautier
- 👤 Pierre-Yves Urena
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:25
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
192 words
A Reloadable Logic Array or RLA comprising: a plurality of electrically isolated word lines carrying word signals; a plurality of electrically isolated bit lines carrying bit signals; said word and bit lines together forming a first matrix of non-conductive intersections; a plurality of input lines carrying digital input signals; a plurality of output lines carrying output signals; said input and output lines together forming a second matrix of non-conductive intersections; a plurality of reprogrammable logic fuses disposed at each couple of said first and second matrixes of non-conductive intersections, at least one of said reprogrammable logic fuses including: a static RAM cell biased between first and second voltages and provided with first and second common nodes to store data therein; a first FET device having a first source electrode connected to one said bit line, a first drain electrode connected to said first common node, and a first gate electrode connected tot he corresponding said word line; and a second FET device having a second source electrode connected to said second common node, a second drain electrode connected to said input line, and a second gate electrode connected to said output line.
Claim 2
Dependent Claim
192 words
A Reloadable Logic Array or RLA comprising: a plurality of electrically isolated word lines carrying word signals; a plurality of electrically isolated bit lines carrying bit signals; said word and bit lines together forming a first matrix of non-conductive intersections; a plurality of input lines carrying digital input signals; a plurality of output lines carrying output signals; said input and output lines together forming a second matrix of non-conductive intersections; a plurality of reprogrammable logic fuses disposed at each couple of said first and second matrixes of non-conductive intersections, at least one of said reprogrammable logic fuses including: a static RAM cell biased between first and second voltages and provided with first and second common nodes to store data therein; a first FET device having a first source electrode connected to one said bit line, a first drain electrode connected to said first common node, and a first gate electrode connected tot he corresponding said word line; and a second FET device having a second source electrode connected to said second common node, a second drain electrode connected to said input line, and a second gate electrode connected to said output line.
Claim 3
Dependent Claim
296 words
A Reloadable Programmable Logic Array or RPLA comprising: a) a logic AND array including: a plurality of first electrically isolated word lines carrying first word signals; a plurality of first electrically isolated bit lines carrying first bit signals; said first word and bit lines together forming a first matrix of non-conductive intersections; a plurality of first input lines carrying first digital input signals; a plurality of first output lines carrying first output signals; said first input and output lines together forming a second matrix of non-conductive intersections; b) a logic OR array including; a plurality of second electrically isolated word lines carrying second word signals; a plurality of second electrically isolated bit lines carrying second bit signals; said second word and bit lines together forming a third matrix of non-conductive intersections; a plurality of second input lines carrying second digital input signals; a plurality of second output lines carrying output signals; said second input and output lines together forming a fourth matrix of non-conductive intersections; c) a plurality of reprogrammable logic fuses disposed at each respective couple of said first and second and said third and fourth intersections, at least one of said reprogrammable logic fuses in the AND array and in the OR array comprising: a static RAM cell biased between first and second voltages having first and second common nodes to store control data therein; a first FET device having a first source electrode connected to one said bit line, a first drain electrode connected to said first common node, and a first gate electrode connected to the corresponding said word line; and a second FET device having a second electrode connected to said second common node, a third electrode connected to said input line, and a fourth electrode connected to said output line.
Claim 4
Dependent Claim
296 words
A Reloadable Programmable Logic Array or RPLA comprising: a) a logic AND array including: a plurality of first electrically isolated word lines carrying first word signals; a plurality of first electrically isolated bit lines carrying first bit signals; said first word and bit lines together forming a first matrix of non-conductive intersections; a plurality of first input lines carrying first digital input signals; a plurality of first output lines carrying first output signals; said first input and output lines together forming a second matrix of non-conductive intersections; b) a logic OR array including; a plurality of second electrically isolated word lines carrying second word signals; a plurality of second electrically isolated bit lines carrying second bit signals; said second word and bit lines together forming a third matrix of non-conductive intersections; a plurality of second input lines carrying second digital input signals; a plurality of second output lines carrying output signals; said second input and output lines together forming a fourth matrix of non-conductive intersections; c) a plurality of reprogrammable logic fuses disposed at each respective couple of said first and second and said third and fourth intersections, at least one of said reprogrammable logic fuses in the AND array and in the OR array comprising: a static RAM cell biased between first and second voltages having first and second common nodes to store control data therein; a first FET device having a first source electrode connected to one said bit line, a first drain electrode connected to said first common node, and a first gate electrode connected to the corresponding said word line; and a second FET device having a second electrode connected to said second common node, a third electrode connected to said input line, and a fourth electrode connected to said output line.
Claim 5
Dependent Claim
17 words
The RPLA of claim 2 wherein each of said static RAM cells is comprised of four FETs.
Claim 6
Dependent Claim
40 words
The RPLA of claim 3 wherein all said FET devices forming the RLFs of said AND array are of a first type of conductivity and all said FET devices of said OR array are of a second type of conductivity.
Claim 7
Dependent Claim
24 words
The RPLA of claim 2 wherein each of said static RAM cells is comprised of two cross-coupled FETs of different types of conductivity pairs.
Claim 8
Dependent Claim
26 words
The RPLA of claim 5 and further including sense amplifier/latch means for making said second input signals have an opposite polarity to said first output signals.
Claim 9
Dependent Claim
56 words
The RPLA of claim 6 and further comprising clamping means for clamping: a) said first and second input lines to the high power supply voltage minus the threshold voltage of said FET devices; and b) said first and second output lines to the high power supply voltage minus twice the threshold voltage of said FET devices.
Claim 10
Dependent Claim
21 words
The RPLA of claim 7 further comprising output sense amplifier/latch means for amplifying and latching said second output signals before use.
Claim 11
Dependent Claim
21 words
The RPLA of claim 8 wherein said sense amplifier/latch means and output sense amplifier latch means are of the clocked type.
Claim 12
Dependent Claim
17 words
The RPLA of claim 2, wherein said second input signals are derived from said first output signals.
References Cited (Backward Citations)
US3560764A
Cited
US3593317A
Cited
US4177452A
Cited
US4617649A
Cited
US4617649B1
Cited
US4613958A
Cited
US4660177A
Cited
US4887239A
Cited
US4779226A
Cited
US4768172A
Cited
US4845676A
Cited
US4796229A
Cited
US4694425A
Cited
US4791603A
Cited
US4876466A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |