Seven transistor content addressable memory (CAM) cell

Claim 1

A content addressable memory including a pair of column lines (54, 56) upon which information to be matched with the contents of said memory is placed, said memory being driven by a clock such that during particular clock phase a ROW line (50) and a MATCH line (52) are precharged and both column lines are discharged, a memory cell characterized by: a supply voltage (Vcc): a first transistor (M1); a second transistor (M2); a third transistor (M3); a fourth transistor (M4); said first, second, third and fourth transistors being connected to each other and to said supply voltage (Vcc) to thereby form a cross-coupled inverter storage device; a fifth transistor (M5); a sixth transistor (M6); and, a seventh transistor (M7) that acts as a "reversible diode"; said fifth and a sixth transistors being connected to said "diode" transistor (M7) and between said cross-coupled inverter (M1, M2, M3, M4) and said column lines (54, 56) to thereby form an XOR gate on said column lines (54, 56) and said "diode" transistor (M7); said diode transistor being connected between said fifth and sixth transistors, said ROW line (50) and said MATCH line (52), such that during CAM matches said diode transistor allows charge to be siphoned from said MATCH line (62) and during a write to said CAM cell allows charge to build up.