Content addressable memory cell with shift capability

Claim 1

A memory cell for storing data provided on a load data input terminal and being adapted for comparing data supplied on a compare data input terminal with data stored in said cell and for supplying an output signal on a match data output terminal when the compare data is the same as the data stored in the cell, said memory cell comprising: a. a latch circuit for storing data and having a true output terminal coupled to said load data input terminal and a not true output terminal; b. first means coupled between said match data output terminal and a reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the state of said latch circuit and the compare data; c. second means coupled between said match data output terminal and said reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the inverse state of said latch circuit and the inverse of the compare data; d. said latch circuit further comprising a pair of inverters each of which has an output coupled to the input of the other inverter and wherein one of said inverters is scaled smaller than the other so that the state of said latch circuit is modifiable by changing the state of the true output terminal of said latch circuit; and e. a transistor means serially coupled to said load data input terminal and being responsive to a shift signal when loading data into said memory cell.

Claim 3

A system including P rows by M columns of content addressable memory cells, wherein P and M are integers greater than one, each of said memory cells comprising: a. a latch circuit for storing data and having a not true output terminal and a true output terminal coupled to a first input terminal disposed for receiving data; b. first means coupled between a match data output terminal and a reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the state of said latch circuit and compare data supplied on a second input terminal; c. second means coupled between said match data output terminal and said reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the inverse state of said latch circuit and the inverse of the compare data; and d. each of said memory cells after said first row further including a transistor means serially coupled to said first input terminal and being operative in response to a shift signal for loading data from the memory cell of the same column in the preceding row.

Claim 4

A system including P rows by M columns of content addressable memory cells, wherein P and M are integers greater than one, each of said memory cells comprising: a. a latch circuit for storing data and having a not true output terminal and a true output terminal coupled to a first input terminal disposed for receiving data; b. first means coupled between a match data output terminal and a reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the state of said latch circuit and compare data supplied on a second input terminal; c. second means coupled between said match data output terminal and said reference potential and being disposed for applying the reference potential to said match data output terminal in response to a comparison of the inverse state of said latch circuit and the inverse of the compare data; and d. each of said memory cells after said first row further including a transistor means serially coupled to said first input terminal and being operative in response to a shift signal for loading data from the memory cell of the same column in the preceding row.