US3868642A
Expired / Lapsed
US
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Hierrarchial associative memory system
Assignee: Wincor Nixdorf International GmbH
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Filing: 1972-08-21
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Granted: 1975-02-25
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Expires: 1992-08-21
Abstract
Abstract An associative memory having a non-associative portion for storing data words and an associative portion for storing the associated addresses, whereby a data word in the non-associative portion is triggered when an offered address coincides with the associated address in the associative portion, the memory employing a main associative memory having the data words in its storage cells in non-associative portions thereof and the low value adress digits of the data words in ;the associative portions, and a selection memory embodies as an associative memory having the higher value address digits of the data words written into the main associative memory contained in its storage cells and operable to produce a concidence signal during selection of the storage cell of the selection memory which simultaneously serves to trigger the storage cells of the main associative memory whose contents have the same higher value address digits.
Inventors
- 👤 Harold Sachs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
271 words
Associative memory apparatus in which a non-associative portion stores data words which are respectively accessed when an offered address coincides with the corresponding data address stored in an associative portion, comprising: a main memory including storage cells each having a non-associative portion and an associative portion, said non-associative portions of said cells storing data words and said associative portions of said cells storing the low value address of digits of said data words; an associative pre-selection memory connected to said main memory and including storage cells storing the higher-value address digits of said data words, said preselection memory and said associative portions of said main memory receiving an input address and including means providing coincidence signals when the high and low-value address digits of said data words correspond to said input address, said non-associative portions of said main memory responsive to and accessed by said coincidence signals, a plurality of AND gates, each gate connected between the associative and non-associative portions of a storage cell of said main memory and having an input connected to said associative portion, an output connected to said nonassociative portion, and an input connected to a storage cell of said prE-selection memory, the AND gates associated with storage cells of said non-associative portions which have the same higher-value address digits stored in said pre-selection memory being combined in a group and having a common input connected to the corresponding storage cell of said pre-selection memory and operated to access the non-associative portions connected thereto in response to a coincidence signal from said pre-selection memory and a coincidence signal from one of the associative portions connected thereto.
Claim 2
Dependent Claim
271 words
Associative memory apparatus in which a non-associative portion stores data words which are respectively accessed when an offered address coincides with the corresponding data address stored in an associative portion, comprising: a main memory including storage cells each having a non-associative portion and an associative portion, said non-associative portions of said cells storing data words and said associative portions of said cells storing the low value address of digits of said data words; an associative pre-selection memory connected to said main memory and including storage cells storing the higher-value address digits of said data words, said preselection memory and said associative portions of said main memory receiving an input address and including means providing coincidence signals when the high and low-value address digits of said data words correspond to said input address, said non-associative portions of said main memory responsive to and accessed by said coincidence signals, a plurality of AND gates, each gate connected between the associative and non-associative portions of a storage cell of said main memory and having an input connected to said associative portion, an output connected to said nonassociative portion, and an input connected to a storage cell of said prE-selection memory, the AND gates associated with storage cells of said non-associative portions which have the same higher-value address digits stored in said pre-selection memory being combined in a group and having a common input connected to the corresponding storage cell of said pre-selection memory and operated to access the non-associative portions connected thereto in response to a coincidence signal from said pre-selection memory and a coincidence signal from one of the associative portions connected thereto.
Claim 3
Dependent Claim
185 words
The memory apparatus according to claim 1, wherein said storage cells of said main memory are assigned continuous cell members, each storage cell of said pre-selection memory comprises an associative portion and a non-associative portion storing continuous cell numbers, said non-associative portion of a storage cell of said pre-selection memory storing a cell number which is the highest of the cell numbers associated with the higher value address digits stored in the associative portion of the storage cell of the pre-selection memory, increased by 1, and which is simultaneously the lowest one of the cell numbers associated with the higher value address digits stored in the associative portion of the next storage cell of the pre-selection memory, and means operable during the selection of a storage cell of the pre-selection memory to trigger the storage cells of said main memory which have cell numbers smaller than the cell numbers stored in the non-associative portion of the storage cell of the pre-selection memory but larger than or equal to the cell number stored in the non-associative portion of the preceding storage cell of the selection memory.
Claim 4
Dependent Claim
286 words
The memory apparatus according to claim 2, comprising first and second selection switches, connected to said storage means said first selection switch connected to receive the contents of the non-associative portions of the storage cells of the pre-selection memory and said second selection switch connected to receive the contents of the non-associative portions of the storge cells of the pre-selection memory, said selection switches connected so that during a selection the content of the non-associative portion of a selected storage cell is provided to said second selection switch and the content of the non-associative portion of the preceding storge cell is provided to said first selection switch, first and second decoding circuits connected to said first and second selection switches, respectively, a limit indicator circuit comprising a plurality of single bit memories respectively associated with each storage cell of the main memory and a logic circuit connecting said single bit memories to said decoding circuit and operable to effectively trigger with said decoding circuits each single bit memory whose assigned storage cell in the main memory have a cell number which is smaller than the content of the non-associative portion of the selected storage cell of the pre-selection memory and larger than or equal to the content of the non-associative portion of the preceding storage cell of the pre-selection memory, AND gates associated with said storage cells of said main memory connected to said single bit memories so that one of said AND gates provides an output signal for triggering the non-associative portion of a storage cell of said main memory whose corresponding single bit memory is set and which recieves a coincidence signal from the associative portion of the storage cell of said main memory.
Claim 5
Dependent Claim
151 words
The memory apparatus according to claim 3, wherein said limit indicator circuit comprises a plurality of OR gates, a plurality of NAND gates, and a plurality of other AND gates, each of said single bit memories having a setting input and an output, said setting input connected to the output of one of said other AND gates and said output connected to the input of a respective first-mentioned AND gate and to an input of one of said OR gates, said OR gates each having another inpUt connected to said first decoding circuit and an output connected to an input of said other AND gate, said NAND gate having an input connected to said second decoding circuit and an output connected to another input of said other AND gate, said other AND gate having a further input for receiving a clock pulse providing the setting time of said single bit memories.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-24 | 1978-08-26 | 1979-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-24 | 1982-08-26 | 1983-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-24 | 1986-08-26 | 1987-02-25 | $7700.00 | Window Closed / Lapsed |