Multimatch processing system

Claim 2

A multimatch system for processing the results of matching signals supplied by a memory also supplying operating control signals, comprising: means for distributing said memory signals, including a plurality of terminals, each supplied with one of said memory signals; a plurality of first AND gates, each having an output and a plurality of inputs, one input of each gate connected to a respective one of said terminals, said gate outputs arranged in pluralities of firSt and second groups of signal transmission paths, each of said first path groups having a first preselected number of paths connected to a corresponding number of said outputs of said first AND gates, each of said second path groups having a second preselected number of paths equal to said first preselected number of paths in each of said first path groups, each of said second path groups having each path of each group connected to a corresponding path in a different one of said first path groups; a plurality of second AND gates, each having an output and two inputs of which last-mentioned inputs one is coupled to one of said first signal path groups; a plurality of third AND gates, each including an output and two inputs of which last-mentioned inputs one is coupled to one of said second signal path groups; said first AND gates having a number eqUal to the product of the number of said second AND gates multiplied by the number of said third AND gates; first logic means supplying a control signal to he the second inputs of said second AND gates and coupling said second AND gate outputs to second inputs of said first AND gates included in different groups thereof; each of said last-mentioned different first AND gate groups having said outputs thereof connected to one of said first signal path groups; and second logic means coupling said third AND gate outputs to third inputs of said first AND gates included in a further different groups thereof, each of said last-mentioned further different first AND gate groups having said outputs thereof connected to each of said second signal path groups; second inputs of said second and third AND gates and said first and second logic means activated by said memory control signals in such predetermined manner as to record alternately in said first and second logic means the occurrences and positions of memory matching signals effective at said distributing means terminals.

Claim 3

The system according to claim 1 in which said first and second logic means are so activated by said memory control signals that a first match signal is recorded in said first logic means, a second match signal is recorded in said second logic means, and thereafter the respective match signals are alternately recorded in said first and second logic means.

Claim 4

The system according to claim 1 in which said second AND gates comprise a number m, said third AND gates comprise a number n, and said memory signals comprise a number equal to the product of m times n, where m and n are integers.

Claim 5

The system according to claim 1 in which said memory signals comprise an n2 number and said second and third AND gates combined comprise a 2n number where n is an integer.

Claim 6

The system according to claim 1 in which said signal distributing means includes a plurality of OR gates each having a plurality of inputs connected to one path group of said first path groups and an output connected to said one input of one of said second second gates.

Claim 7

The system according to claim 1 in which said signal distributing means includes a plurality of OR gates, each having a plurality of inputs connected to one path group of said second path groups and an output connected to said one input of one said third AND gates.

Claim 8

The system according to claim 1 in which said signal distributing means includes a plurality of first OR gates, each having a plurality of outputs connected to one path group of said first path groups and an output connected to said one input of one of said second AND gates; and a plurality of second OR gates, each of having a plurality of inputs connected to one path group of said said second path groups and an output connected to said one input of one of said third AND gates.

Claim 9

The system according to claim 7 in which said first OR gates comprise a number m, said second OR gates comprise a number n, and said first AND gates comprise a number number equal to the product of m times n, where m and n are integers.

Claim 10

The system according to claim 1 in which said first logic means includes a plurality of flip-flop circuits, each having at least one input and one output, each of said last-mentioned circuits having said one input connected to said output of one of said second AND gates and said one output connected to said second inputs of said first AND gates included in one of said different first AND gate groups, said flip-flop circuits recording match signals effective in said second AND gate outputs.

Claim 11

The system according to claim 1 in which said second logic means includes a plurality of flip-flop circuits, each having at least one input and one output, each of said last-mentioned circuits having said one input connected to said output of one of said third AND gates and said one output connected to said third inputs of said first AND gates and said one output connected to said third inputs of said first AND gates included in one of said further different first AND groups, said flip-flop circuits recording match signals effective in said third And gates outputs.

Claim 12

The system according to claim 1 in which said first logic means includes a plurality of first flip-flop circuits, each having at least one input and one output, each of said last-mentioned circuits having said one input connected to said output of one of said second AND gates and said one output connected to said second inputs of said first AND gates included in one of said different AND gate groups, said first flip-flop circuits recording match signals effective in said second AND gate outputs; and said second logic means includes a plurality of second flip-flop circuits, each having at least one input and one output, each of said last-mentioned circuits having said one input connected to said output of one of said third AND gates and said output connected to said third inputs of said first AND gates included in one of said further different first AND gate groups, said second flip-flop circuits recording match signals effective in said third AND gate outputs.

Claim 13

The system according to claim 11 in which said first flip-flop circuits comprise an m number, said second flip-flop circuits comprise an n number, and said memory signals comprise a number equal to the product of m times n, where m and n are integers.

Claim 14

The system according to claim 11 in which said flip-flop circuits comprise an m number, said second flip-flop circuits comprise an n number, and said first AND gates comprise a number equal to the product of m times n, where m and n are integers.

Claim 15

The system according to claim 1 in which said first logic means comprises: a plurality of fourth AND gates, each having an output and a plurality of inputs, one input of each of four of said last-mentioned AND gates receiving one of said memory control signals; a plurality of first OR gates, each having an output connected to said second inputs of said first AND gates included in one of said different groups thereof, a first input connected to the output of one of said four to of said fourth AND gates, and a second input receiving one of said memory control signals; a plurality of flip-flop circuits, each having two inputs and two outputs; a first of said flip-flop circuits having one of said inputs thereof connected to the output o of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four to of said fourth AND gates, a first of said outputs thereof connected to a second input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a second input of each of second, third and fourth AND gates included in said four of said fourth AND gates and to a first input oF a fifth of said fourth AND gates; a second of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four to of said fourth AND gates, a first of said outputs thereof connected to a third input of said last-mentined one AND gate, and a second of said outputs thereof connected to a third input of each of said third and fourth AND gates included in said four of said fourth AND gates and to a second input of said fifth of said fourth AND gates; a third of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a last-mentioned one of said four of said fourth AND gates, a first of said outputs thereof connected to a fourth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said fourth of said four of said fourth AND gates and to a third input of said fifth of said fourth AND gates; and a fourth of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said fifth of said fourth AND gates; said fifth of said fourth AND gates having an output connected to said second logic means.

Claim 16

The system of according to claim 1 in which said second logic means comprises: a plurality of fourth AND gates, each having an output and a plurality of inputs, one input of each of four of said last-mentioned gates receiving one of said memory control signals; a plurality of OR gates, each having an output connected to said third inputs of said first AND gates included in each of said further different groups thereof, a first input connected to the output of one of said four of said fourth AND gates, and a second input receiving one of said memory control signals; a plurality of flip-flop circuits, each having two inputs and two outputs; a first of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates and a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs of thereof connected to a second input of said last-mentioned one fourth AND gate and a second of said outputs thereof connected to a second input of said second, third and fourth AND gates included in said four of said fourth AND gates, said last-mentioned output also connected to a first input of a fifty of said fourth AND gates; A second of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a third input of said last-mentioned one fourth AND gate, and a second of said outputs thereof connected to a third input of each of said third and fourth AND gates included in said four of said fourth AND gates, said last-mentioned output also connected to a second input of said fifty of said fourth AND gates; a third of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected of the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fourth input of said last-mentioned One of said fourth AND gate, and a second of said outputs thereof connected to a fourth input of said fourth of said four of fourth AND gates, and last-mentioned output also connected to a third input fifth of said fourth AND gates; and a fourth of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four or said fourth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one of said fourth AND gates; and a second of said outputs thereof connected to a fourth input of said fifth of said fourth AND gates; a first delay network having an input connected to the output of said last-mentioned fifty of said fourth AND gates; a first signal polarity inverter having an input connected to the output of said last-mentioned network; a further AND gate having one input connected to the output of said first inverter and a second input connected to the output of said last-mentioned fifth of said fourth AND gates; a second signal polarity inverter having an input connected to the output of said further AND gate and an output supplying a control signal to said first logic means; a further OR gate having a first input connected to the output of said further AND gate and a second input for receiving one of said memory control signals; and a second delay network having an input connected to the input of said further OR gate and an output supplying a control signal to said distributing means and said second logic means.

Claim 17

A multimatch system for processing the results of matching signals supplied by a memory also supplying operating control signals, comprising: means for distributing said memory signals, including a plurality of terminals, each supplied with one of said memory signals; a plurality of first AND gates, each having an output and a plurality of inputs, one input of each gate connected to a respective one of said terminals, said gate outputs arranged in pluralities of first and second groups of signal transmission paths; each of said first path groups having a first preselected number of paths connected to a corresponding number of said outputs of said first AND gates; each of said second path groups having a second preselected number of paths equal to said first preselected number of paths in each of said first path groups; each of said second path groups having each path of each group connected to a corresponding path in a different one of said first path groups; a plurality of first OR gates, each having an output and a plurality of inputs connected to said paths in one group of said first path groups; a plurality of second AND gates, each having an output and two inputs of which said last-mentioned inputs one is connected to the output of a corresponding one of said first OR gates; a plurality of second OR gates, each having an input and a plurality of inputs connected to said paths in one group of said second path groups; a plurality of third AND gates, each having an output and two inputs of which said last-mentioned inputs one is connected to the output of one of said second OR gates; first logic means connecting the outputs of said second AND gates to second inputs of said first AND gates, including; a plurality of fourth AND gates, each having an output and a plurality of inputs, a plurality of third OR gates, each having an output connected to second inputs of said first AND gates having outputs arranged in one of said first path groups, a first input connected to the output of one of four of said fourth AND gates, and a second input receiving one of said memory control signals, a plurality of first flip-flop circuits, each having two inputs and two outputs, containing; a first of said first flip-flop circuits having one of Said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of fourth AND gates, a first of said outputs thereof connected to a second input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a second input of each of a second, a third and a fourth of said four of said fourth AND gates and to a first input of a fifth of said fourth AND gates; a second of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a third input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a third input of each of said third and fourth AND gates included in said fourth of said fourth AND gates and to a second input of said fifth of said fifth of said fourth AND gates; a third of said first flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fourth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said fourth in said four of said fourth AND gates and to a third input of said fifth of said fourth AND gates; and a fourth of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said input of said fourth AND gates; said output of said last-mentioned fifty of said fourth AND gates connected to second inputs of said second AND gates; and second logic means connecting the outputs of said third AND gates to third inputs of said first AND gates, including; a relatively plurality of fifty and AND gates, each having an output and a plurality of inputs, one input of each of four of said fifth AND gates receiving one of said memory control signals, a plurality of fourth OR gates, each having an output connected to said third inputs of said first AND gates having outputs arranged in one of said second path groups, a first input connected to the output of said four of said fifth AND gates, a plurality of second flip-flop circuits, each having two inputs and two outputs, consisting of: a first of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs threrof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said outputs thereof connected to a second input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a second input of each of said second, third and fourth AND gates included in said four of said fifth AND gates and to a first input of a fifth of said fifth AND gates; a second of said second flip-flop circuits having one of said inputs connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said for of said fifth AND gates, a first of said outputs thereof connected to a third input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a third input of each of said third and fouRth AND gates included in said four of said fifth AND gates and to a second input of said fifth of said fifth AND gates; a third of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said output thereof connected to a fourth input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a fourth input of said fourth of said four of said fifth AND gates and to a third input of said fifth of said fifth AND gates; and a fourth of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a fourth input of said fifth of said fifth AND gates; a first delay network having an input connected to the output of said last-mentioned fifth of said fifth AND gates; a first signal polarity inverter having an input connected to the output of said last-mentioned network; a further AND gate having one input connected to the output of said first inverter and a second input connected to the output of said last-mentioned fifth of said fifth AND gates; a second signal polarity inverter having an input connected to the output of said further AND gate and an output supplying a control signal of first inputs of said four of said fourth AND gates; a further OR gate having

Claim 18

A multimatch system for processing the results of matching signals supplied by a memory also supplying operating control signals, comprising: means for distributing said memory signals, including a plurality of terminals, each supplied with one of said memory signals; a plurality of first AND gates, each having an output and a plurality of inputs, one input of each gate connected to a respective one of said terminals, said gate outputs arranged in pluralities of first and second groups of signal transmission paths; each of said first path groups having a first preselected number of paths connected to a corresponding number of said outputs of said first AND gates; each of said second path groups having a second preselected number of paths equal to said first preselected number of paths in each of said first path groups; each of said second path groups having each path of each group connected to a corresponding path in a different one of said first path groups; a plurality of first OR gates, each having an output and a plurality of inputs connected to said paths in one group of said first path groups; a plurality of second AND gates, each having an output and two inputs of which said last-mentioned inputs one is connected to the output of a corresponding one of said first OR gates; a plurality of second OR gates, each having an input and a plurality of inputs connected to said paths in one group of said second path groups; a plurality of third AND gates, each having an output and two inputs of which said last-mentioned inputs one is connected to the output of one of said second OR gates; first logic means connecting the outputs of said second AND gates to second inputs of said first AND gates, including; a plurality of fourth AND gates, each having an output and a plurality of inputs, a plurality of third OR gates, each having an output connected to second inputs of said first AND gates having outputs arranged in one of said first path groups, a first input connected to the output of one of four of said fourth AND gates, and a second input receiving one of said memory control signals, a plurality of first flip-flop circuits, each having two inputs and two outputs, containing; a first of said first flip-flop circuits having one of Said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of fourth AND gates, a first of said outputs thereof connected to a second input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a second input of each of a second, a third and a fourth of said four of said fourth AND gates and to a first input of a fifth of said fourth AND gates; a second of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a third input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a third input of each of said third and fourth AND gates included in said fourth of said fourth AND gates and to a second input of said fifth of said fifth of said fourth AND gates; a third of said first flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fourth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said fourth in said four of said fourth AND gates and to a third input of said fifth of said fourth AND gates; and a fourth of said flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said second AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fourth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one AND gate, and a second of said outputs thereof connected to a fourth input of said input of said fourth AND gates; said output of said last-mentioned fifty of said fourth AND gates connected to second inputs of said second AND gates; and second logic means connecting the outputs of said third AND gates to third inputs of said first AND gates, including; a relatively plurality of fifty and AND gates, each having an output and a plurality of inputs, one input of each of four of said fifth AND gates receiving one of said memory control signals, a plurality of fourth OR gates, each having an output connected to said third inputs of said first AND gates having outputs arranged in one of said second path groups, a first input connected to the output of said four of said fifth AND gates, a plurality of second flip-flop circuits, each having two inputs and two outputs, consisting of: a first of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs threrof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said outputs thereof connected to a second input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a second input of each of said second, third and fourth AND gates included in said four of said fifth AND gates and to a first input of a fifth of said fifth AND gates; a second of said second flip-flop circuits having one of said inputs connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said for of said fifth AND gates, a first of said outputs thereof connected to a third input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a third input of each of said third and fouRth AND gates included in said four of said fifth AND gates and to a second input of said fifth of said fifth AND gates; a third of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said output thereof connected to a fourth input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a fourth input of said fourth of said four of said fifth AND gates and to a third input of said fifth of said fifth AND gates; and a fourth of said second flip-flop circuits having one of said inputs thereof connected to the output of a corresponding one of said third AND gates, a second of said inputs thereof connected to the output of a corresponding one of said four of said fifth AND gates, a first of said outputs thereof connected to a fifth input of said last-mentioned one of said fifth AND gates, and a second of said outputs thereof connected to a fourth input of said fifth of said fifth AND gates; a first delay network having an input connected to the output of said last-mentioned fifth of said fifth AND gates; a first signal polarity inverter having an input connected to the output of said last-mentioned network; a further AND gate having one input connected to the output of said first inverter and a second input connected to the output of said last-mentioned fifth of said fifth AND gates; a second signal polarity inverter having an input connected to the output of said further AND gate and an output supplying a control signal of first inputs of said four of said fourth AND gates; a further OR gate having